Semiconductor device and manufacturing method thereof

• US 9,530,852 B2
• Filed: 07/16/2015
• Issued: 12/27/2016
• Est. Priority Date: 05/12/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Isobe, Atsuo, Sasaki, Toshinari, Koezuka, Junichi, Yamazaki, Shunpei
• Primary Examiner(s): Hossain, Moazzam
• Application Number:
  US14/801,130
• Publication Number:
  US 20150318368A1
• Time in Patent Office: 530 Days
• Field of Search: 257/53
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/425 producing ion implantation
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

It is an object to provide a semiconductor device in which a short-channel effect is suppressed and miniaturization is achieved, and a manufacturing method thereof. A trench is formed in an insulating layer and impurities are added to an oxide semiconductor film in contact with an upper end corner portion of the trench, whereby a source region and a drain region are formed. With the above structure, miniaturization can be achieved. Further, with the trench, a short-channel effect can be suppressed setting the depth of the trench as appropriate even when a distance between a source electrode layer and a drain electrode layer is shortened.

Claims

1. A semiconductor device comprising:

an insulating layer including a first region having a first thickness and a second region having a second thickness smaller than the first thickness, the insulating layer including a trench including a side surface and a bottom surface, the bottom surface being overlapped with the second region;

an oxide semiconductor film which includes a third region, a fourth region and a channel formation region, and which is in contact with the bottom surface and the side surface of the trench and a top surface of the first region;

a source electrode layer and a drain electrode layer which are electrically connected to the third region and the fourth region, respectively;

a gate insulating layer over the oxide semiconductor film, the source electrode layer and the drain electrode layer; and

a gate electrode layer over the gate insulating layer, the gate electrode layer overlapping with the trench,

wherein the channel formation region of the oxide semiconductor film is in contact with the side surface and the bottom surface of the trench,

wherein the third region and the fourth region of the oxide semiconductor film are in contact with the top surface of the first region and an upper end corner portion where the top surface of the first region intersects the side surface of the trench,

wherein the third region and the fourth region have higher impurity concentrations than the channel formation region, and

wherein an end portion of the third region and an end portion of the fourth region are below the top surface of the first region.

2. The semiconductor device according to claim 1,

wherein the trench has a curved surface at a lower end corner portion where the bottom surface of the trench intersects the side surface of the trench, and

wherein a radius of curvature of the lower end corner portion is greater than or equal to 20 nm and less than or equal to 60 nm.

3. The semiconductor device according to claim 1,

wherein thickness of the oxide semiconductor film is greater than or equal to 1 nm and smaller than or equal to 100 nm.

4. The semiconductor device according to claim 1,

wherein parts of the third region and the fourth region overlap with the gate electrode layer.

5. The semiconductor device according to claim 1,

wherein the oxide semiconductor film comprises indium, gallium and zinc.

6. The semiconductor device according to claim 1,

wherein the third region and the fourth region comprise an amorphous oxide semiconductor in a region which has the higher impurity concentrations.

7. A semiconductor device comprising:

a substrate comprising a single crystal silicon;

an insulating layer over the substrate, the insulating layer including a first region having a first thickness and a second region having a second thickness smaller than the first thickness, and the insulating layer including a trench including a side surface and a bottom surface, the bottom surface being overlapped with the second region;

an oxide semiconductor film which includes a third region, a fourth region and a channel formation region, and which is in contact with the bottom surface and the side surface of the trench and a top surface of the first region;

a source electrode layer and a drain electrode layer which are electrically connected to the third region and the fourth region, respectively;

a gate insulating layer over the oxide semiconductor film, the source electrode layer and the drain electrode layer; and

a gate electrode layer over the gate insulating layer, the gate electrode layer overlapping with the trench,

wherein the channel formation region of the oxide semiconductor film is in contact with the side surface and the bottom surface of the trench,

wherein the third region and the fourth region of the oxide semiconductor film are in contact with the top surface of the first region and an upper end corner portion where the top surface of the first region intersects the side surface of the trench,

wherein the third region and the fourth region have higher impurity concentrations than the channel formation region, and

wherein an end portion of the third region and an end portion of the fourth region are below the top surface of the first region.

8. The semiconductor device according to claim 7,

wherein the trench has a curved surface at a lower end corner portion where the bottom surface of the trench intersects the side surface of the trench, and

wherein a radius of curvature of the lower end corner portion is greater than or equal to 20 nm and less than or equal to 60 nm.

9. The semiconductor device according to claim 7,

wherein thickness of the oxide semiconductor film is greater than or equal to 1 nm and smaller than or equal to 100 nm.

10. The semiconductor device according to claim 7,

wherein parts of the third region and the fourth region overlap with the gate electrode layer.

11. The semiconductor device according to claim 7,

wherein the oxide semiconductor film comprises indium, gallium and zinc.

12. The semiconductor device according to claim 7,

wherein the third region and the fourth region comprise an amorphous oxide semiconductor in a region which has the higher impurity concentrations.