Insulated gate semiconductor device having a shield electrode structure and method

• US 9,530,883 B2
• Filed: 01/11/2016
• Issued: 12/27/2016
• Est. Priority Date: 07/21/2014
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Deng, Shengling, Hossain, Zia
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US14/992,106
• Publication Number:
  US 20160126348A1
• Time in Patent Office: 351 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a semiconductor region with a charge balance region on a junction blocking region, which has a lower doping concentration. A trench structure having an insulated shield electrode and an insulated gate electrode is provided in the semiconductor region. The semiconductor device further includes one or more features configured to improve operating performance. The features include terminating the trench structure in the junction blocking region, providing a localized doped region adjoining a lower surface of a body region and spaced apart from the trench structure, disposing a notch proximate to the lower surface of the body region, and/or configuring the insulated shield electrode to have a wide portion adjoining a narrow portion.

Claims

1. A method for forming an insulated gate semiconductor device comprising:

providing a semiconductor region comprising;

a semiconductor substrate;

a first semiconductor layer of a first conductivity type and a first dopant concentration on the semiconductor substrate, and

a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having the first conductivity type, having a second dopant concentration greater than the first dopant concentration;

forming a trench structure disposed in the first semiconductor layer and the second semiconductor layer extending from the major surface, wherein the trench structure comprises;

a trench;

an insulated gate electrode; and

an insulated shield electrode adjacent the insulated gate electrode;

forming a body region of a second conductivity type in the second semiconductor layer extending from the major surface, wherein the trench structure is adjacent the body region;

forming a source region of the first conductivity type in the body region adjacent the trench structure; and

forming a doped region of the second conductivity type in the second semiconductor layer adjacent a lower surface of the body region, wherein a portion of the second semiconductor layer separates the doped region from the trench structure and another portion of the second semiconductor layer separates the doped region from the first semiconductor layer.

2. The method of claim 1, wherein forming the trench structure comprises:

forming a shield electrode comprising a first portion and a second portion, wherein the first portion is wider than the second portion.

3. The method of claim 1, wherein forming the trench structure comprises:

forming the trench having a notch in a sidewall, wherein the notch is oriented substantially inward towards an inner portion of the trench.

4. The method of claim 3, wherein forming the body region comprises disposing a lower surface of the body region and the notch proximate to each other.

5. The method of claim 1, wherein providing the semiconductor region comprises providing the second dopant concentration at least 90% greater than the first dopant concentration.

6. The method of claim 1, wherein providing the semiconductor region comprises providing the second dopant concentration in a range from about 150% to about 750% greater than the first dopant concentration.

7. A method for forming an insulated gate semiconductor device comprising:

providing a region of semiconductor material comprising;

a semiconductor substrate;

a first semiconductor layer of a first conductivity type and a first dopant concentration on the semiconductor substrate; and

a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having the first conductivity type, having a second dopant concentration greater than the first dopant concentration, and having a major surface;

forming a first trench structure in the first semiconductor layer and the second semiconductor layer extending from the major surface, and wherein the first trench structure comprises;

a first trench terminating within the first semiconductor layer;

a first insulated gate electrode; and

a first insulated shield electrode below the first insulated gate electrode;

forming a second trench structure in the first semiconductor layer and the second semiconductor layer extending from the major surface, wherein the second trench structure and the first trench structure are laterally spaced apart, and wherein the second trench structure comprises;

a second trench terminating within the first semiconductor layer;

a second insulated gate electrode; and

a second insulated shield electrode below the second insulated gate electrode, wherein the second semiconductor layer is a continuous layer extending between the first trench and the second trench;

forming a body region of a second conductivity type in the second semiconductor layer extending from the major surface, wherein the body region is adjacent the first trench structure and adjacent the second trench structure;

forming a first source region of the first conductivity type in the body region adjacent the first trench structure; and

forming a second source region of the first conductivity type in the body region adjacent the second trench structure.

8. The method of claim 7, further comprising:

forming a first doped region of the second conductivity type in the second semiconductor layer adjacent a lower surface of the body region, wherein a portion of the second semiconductor layer separates the first doped region from the first trench structure, another portion of the second semiconductor layer separates the first doped region from the second trench structure, and a further portion of the second semiconductor layer separates the first doped region from the first semiconductor layer.

9. The method of claim 8 further comprising:

forming a plurality of second doped regions of the second conductivity type between the first doped region and the major surface and spaced apart from the first and second trench structures, wherein the first doped region is partially within the body region and partially within the second semiconductor layer.

10. The method of claim 7, wherein providing the region of semiconductor material comprises providing the second dopant concentration at least 90% greater than the first dopant concentration.

11. The method of claim 7, wherein providing the region of semiconductor material comprises providing the second dopant concentration in a range from about 150% to about 750% greater than the first dopant concentration.

12. The method of claim 7, wherein providing the region of semiconductor material comprises providing the second dopant concentration in a range from about 250% to about 700% greater than the first dopant concentration.

13. The method of claim 7, wherein providing the region of semiconductor material comprises:

providing the first dopant concentration in a range from about 5.0×

10¹⁵ atoms/cm³ to about 1.0×

10¹⁶ atoms/cm³; and

providing the second dopant concentration in a range from of about 2.0×

10¹⁶ atoms/cm³ to about 4.0×

10¹⁶ atoms/cm³.

14. The method of claim 7, wherein providing the region of semiconductor material comprises:

providing the first semiconductor layer having a thickness from about 4 microns to about 5 microns; and

providing the second semiconductor layer having a thickness from about 3.5 microns to about 4.5 microns.

15. The method of claim 7, wherein forming first trench structure comprises forming the first trench having a sidewall profile with a notch oriented substantially inward towards an inner portion of the first trench, wherein the notch and a lower surface of the body region are adjacent.

16. A method for forming an insulated gate semiconductor device comprising:

providing a region of semiconductor material comprising a semiconductor substrate, a first semiconductor layer of a first conductivity type and a first dopant concentration adjacent the semiconductor substrate, and a second semiconductor layer adjacent the first semiconductor layer, the second semiconductor layer having the first conductivity type, having a second dopant concentration greater than the first dopant concentration, and having a major surface;

forming a trench structure having a trench structure first portion and a trench structure second portion in cross-sectional view, wherein the second semiconductor layer is a continuous layer extending between the trench structure first portion and the trench structure second portion in cross-sectional view, and wherein the trench structure comprises;

a trench extending from the major surface terminating within the first semiconductor layer;

an insulated gate electrode; and

an insulated shield electrode below the insulated gate electrode;

forming a body region of a second conductivity type in the second semiconductor layer extending from the major surface, wherein the body region is adjacent to the trench structure first portion and adjacent to the trench structure second portion; and

forming a source region of the first conductivity type in the body region, wherein the source region comprises a source region first portion adjacent the trench structure first portion and a source region second portion adjacent the trench structure second portion in cross-sectional view.

17. The method of claim 16, further comprising:

forming a first doped region of the second conductivity type in the second semiconductor layer adjacent a lower surface of the body region, wherein a portion of the second semiconductor layer separates the first doped region from the trench structure first portion, another portion of the second semiconductor layer separates the first doped region from the trench structure second portion, and a further portion of the second semiconductor layer separates the first doped region from the first semiconductor layer.

18. The method of claim 16, wherein providing the region of semiconductor material comprises providing the second dopant concentration at least 90% greater than the first dopant concentration.

19. The method of claim 16, wherein providing the region of semiconductor material comprises providing the second dopant concentration in a range from about 100% to about 800% greater than the first dopant concentration.

20. The method of claim 16, wherein providing the region of semiconductor material comprises:

providing the first dopant concentration in a range from about 5.0×

10¹⁵ atoms/cm³ to about 1.0×

10¹⁶ atoms/cm³; and

providing the second semiconductor layer having a dopant concentration in a range from of about 2.0×

10¹⁶ atoms/cm³ to about 4.0×

10¹⁶ atoms/cm³.