Integrated circuit device

• US 9,530,945 B2
• Filed: 11/25/2013
• Issued: 12/27/2016
• Est. Priority Date: 02/06/1998
• Status: Expired due to Fees

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Badehi, Avner
• Primary Examiner(s): Graybill, David E
• Application Number:
  US14/089,539
• Publication Number:
  US 20140077395A1
• Time in Patent Office: 1,128 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/82 to produce devices, e.g. integrated circuits, each consisting of a plurality of components
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 31/02002 : Arrangements for conducting electric current to or from the device in operations
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 31/02164 : for shielding light, e.g. light blocking layers, cold shields for infrared detectors
• CPC Class Codes: H01L 31/02327 : the optical elements being integrated or being directly associated to the device, e.g. back reflectors optical coatings H01L31/0216
• CPC Class Codes: H01L 31/125 : Composite devices with photosensitive elements and electroluminescent elements within one single body
• CPC Class Codes: H01L 31/186 : Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
• CPC Class Codes: H01L 33/0095 : Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/44 : characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/483 : Containers
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/52 : Encapsulations
• CPC Class Codes: H01L 33/56 : Materials, e.g. epoxy or silicone resin
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

An integrally packaged optronic integrated circuit device including an integrated circuit die containing at least one of a radiation emitter and radiation receiver and having a transparent packaging layer overlying a surface of the die, the transparent packaging layer having an opaque coating adjacent to edges of the layer.

Claims

1. A packaged optoelectronic chip comprising:

a die including at least one of a radiation emitter and a radiation receiver, the die including a first surface, a second opposed surface, edge surfaces extending in a direction away from the first surface, and bond pads exposed at the first surface of the die;

a transparent packaging layer overlying one of the first and second surfaces of the die, the transparent packaging layer having an inner surface facing the die, an opposed outer surface, and a plurality of edges, the plurality of edges defining a step and each of the plurality of edges having surfaces facing an exterior of the chip package, at least some of the plurality of edges extending at least partially between the inner and outer surfaces of the transparent packaging layer, the at least some of the plurality of edges including a first edge surface bounding an exterior perimeter of the inner surface and a second edge surface bounding an exterior perimeter of the outer surface; and

an opaque layer covering a portion of the transparent packaging layer adjacent at least one of the plurality of edges of the transparent packaging layer.

2. The packaged optoelectronic chip as claimed in claim 1, wherein the opaque layer covers the plurality of edges defining the step that extend along the opposed outer surface and the second edge surface of the packaging layer.

3. The packaged chip as claimed in claim 1, wherein at least one of the first and second surfaces of the die has a longest dimension and a major surface of the transparent packaging layer has a longest dimension which exceeds the longest dimension of the die.

4. The packaged chip as claimed in claim 3, wherein the longest dimension of the transparent packaging layer does not exceed the longest dimension of the one of the first and second surfaces of the die by more than 10%.

5. The packaged chip as claimed in claim 3, wherein the longest dimension of the transparent packaging layer does not exceed the longest dimension of the one of the first and second surfaces of the die by more than 5%.

6. The packaged chip as claimed in claim 1, wherein the first surface of the die is a front surface, and the at least one of the radiation emitter or a radiation receiver is disposed adjacent the front surface, and the packaged chip further comprises an insulating layer overlying the second surface of the die.

7. The packaged chip as claimed in claim 1, further comprising:

an insulating layer having insulated outer edge surfaces and being spaced apart from the transparent packaging layer; and

a plurality of contacts extending along the insulated edge surfaces of the insulating layer and exposed at an exterior of the packaged optoelectronic chip, the plurality of contacts electrically connected to the die,

the die positioned between the insulating layer and the transparent packaging layer.

8. The packaged chip as claimed in claim 1, further comprising contacts electrically connected to the die.

9. The packaged chip as claimed in claim 8, wherein said contacts are solderable contacts.

10. The packaged chip as claimed in claim 1 wherein said at least one of a radiation emitter or a radiation receiver is an imaging device.

11. The packaged chip as claimed in claim 1, further comprising an array of microlenses operatively associated with the die.

12. The packaged chip as claimed in claim 11, wherein said microlenses are incorporated in said transparent packaging layer.

13. The packaged chip as claimed in claim 1, further comprising an optical grating operatively associated with the die.

14. The packaged chip as claimed in claim 13, wherein said optical grating is incorporated in said transparent packaging layer.

15. The packaged chip as claimed in claim 1, further comprising a wavelength-selective filter operatively associated with the die.

19. The packaged optoelectronic chip of claim 7, wherein the contacts have an outermost edge surface aligned with the inner surface of the transparent packaging layer in a direction perpendicular to a direction the inner surface of the transparent packaging layer extends.

16. A packaged optoelectronic chip comprising:

a die including an active front surface, a rear surface, and at least one of a radiation emitter and a radiation receiver;

a transparent packaging layer overlying the active front surface of the die, the transparent packaging layer having an outer surface facing away from the die, and an edge extending away from the outer surface;

an insulating layer having a bottom surface and an opposed top surface facing the rear surface of the die, the insulated layer spaced apart from the transparent packaging layer and having an insulated edge surface extending between the top and bottom surfaces; and

a plurality of contacts extending along the insulated edge surface and exposed at an exterior portion of the packaged optoelectronic chip, the plurality of contacts electrically connected with the die and spaced apart from the transparent packaging layer,

wherein at least a first portion of the outer surface is exposed at another exterior portion of said packaged optoelectronic chip and an opaque layer covers at least a second portion of the outer surface near the edge.

17. The packaged chip as claimed in claim 16, wherein the die has a face and edges extending away from the face, the transparent packaging layer extends beyond at least one of the edges of the die, and the opaque layer covers at least a portion of the transparent packaging layer between the at least one of the edges of the die and the edge of the transparent packaging layer.

18. The packaged chip as claimed in claim 16, wherein a face of the die has a longest dimension and a major surface of the transparent packaging layer has a longest dimension which exceeds the longest dimension of the surface of the die by no more than 20%.

20. The packaged optoelectronic chip of claim 16, wherein the die is positioned between the insulating layer and the transparent packaging layer, and the insulating layer has insulated edge surfaces, the packaged chip further comprising:

a plurality of contacts extending along the insulated edge surfaces of the insulating layer and electrically connected to the die, wherein the contacts have an outermost edge surface aligned with an inner surface of the transparent packaging layer in a direction perpendicular to a direction the inner surface of the transparent packaging layer extends and wherein the opaque layer further covers at least a portion of the edge of the transparent packaging layer.