Power efficient multiplexer
First Claim
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1. A circuit, comprising:
- a transmission gate structure including a plurality of input nodes and an output node operable to output a signal; and
a stacked inverter including;
an inverter input node coupled to the output node;
a low-to-high transition leg directly coupled to the output node to receive the signal and comprising a first number of transistors;
a high-to-low transition leg directly coupled to the output node to receive the signal and comprising a second number of transistors that is different relative to the first number of transistors; and
an inverter output node coupled to the low-to-high transition leg and to the high-to-low transition leg.
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Abstract
A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.
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Citations
20 Claims
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1. A circuit, comprising:
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a transmission gate structure including a plurality of input nodes and an output node operable to output a signal; and a stacked inverter including; an inverter input node coupled to the output node; a low-to-high transition leg directly coupled to the output node to receive the signal and comprising a first number of transistors; a high-to-low transition leg directly coupled to the output node to receive the signal and comprising a second number of transistors that is different relative to the first number of transistors; and an inverter output node coupled to the low-to-high transition leg and to the high-to-low transition leg. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A circuit, comprising:
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a plurality of input nodes; an intermediate node; a plurality of transmission gates coupled to a respective one of the plurality of input nodes and coupled to the intermediate node that is operable to receive a signal from at least one of the transmission gates; and a stacked inverter including; an inverter input node coupled to the intermediate node; a low-to-high transition leg directly coupled to the intermediate node to receive the signal and comprising a first number of transistors; a high-to-low transition leg directly coupled to the intermediate node to receive the signal and comprising a second number of transistors that is different relative to the first number of transistors; and an inverter output node coupled to the low-to-high transition leg and to the high-to-low transition leg. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A circuit, comprising:
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a latch; a transmission gate structure including a plurality of input nodes, an output node operable to output a signal, and a plurality of control nodes coupled to the latch; and a stacked inverter including; an inverter input node coupled to the output node; a low-to-high transition leg directly coupled to the output node to receive the signal and comprising a first number of transistors; a high-to-low transition leg directly coupled to the output node to receive the signal and comprising a second number of transistors that is different relative to the first number of transistors; and an inverter output node coupled to the low-to-high transition leg and to the high-to-low transition leg. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification