Power efficient multiplexer

• US 9,531,361 B2
• Filed: 10/13/2015
• Issued: 12/27/2016
• Est. Priority Date: 06/08/2004
• Status: Active Grant

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Holding 81 LLC (Intellectual Ventures LLC)
• Inventors: Masleid, Robert Paul
• Primary Examiner(s): Chang, Daniel D
• Application Number:
  US14/882,264
• Publication Number:
  US 20160036424A1
• Time in Patent Office: 441 Days
• Field of Search: 326/133, 326/119, 326/121, 326/122, 326/83, 327/415, 327/416, 327407-410
• US Class Current: 1/1
• CPC Class Codes: H03K 17/005 with several inputs only
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 2005/00156 using opamps, comparators, voltage multipliers or other analog building blocks
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 5/13 Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A power efficient multiplexer. In accordance with a first embodiment, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.

Claims

1. A circuit, comprising:

a transmission gate structure including a plurality of input nodes and an output node operable to output a signal; and

a stacked inverter including;

an inverter input node coupled to the output node;

a low-to-high transition leg directly coupled to the output node to receive the signal and comprising a first number of transistors;

a high-to-low transition leg directly coupled to the output node to receive the signal and comprising a second number of transistors that is different relative to the first number of transistors; and

an inverter output node coupled to the low-to-high transition leg and to the high-to-low transition leg.

2. The circuit of claim 1, wherein the first number of transistors is greater than the second number of transistors.

3. The circuit of claim 1, wherein the first number of transistors is less than the second number of transistors.

4. The circuit of claim 1, wherein the first number of transistors comprises p-type transistors, and wherein each p-type transistor includes a respective gate coupled to the inverter input node.

5. The circuit of claim 1, wherein the second number of transistors comprises n-type transistors, and wherein each n-type transistor includes a respective gate coupled to the inverter input node.

6. The circuit of claim 1, wherein the stacked inverter is operable to provide at the inverter output node an inverted version of an input value at a selected one of the plurality of input nodes.

7. The circuit of claim 1, wherein the transmission gate structure further comprises:

a first transmission gate coupled between a first input node of the plurality of input nodes and the output node; and

a second transmission gate coupled between a second input node of the plurality of input nodes and the output node.

8. A circuit, comprising:

a plurality of input nodes;

an intermediate node;

a plurality of transmission gates coupled to a respective one of the plurality of input nodes and coupled to the intermediate node that is operable to receive a signal from at least one of the transmission gates; and

a stacked inverter including;

an inverter input node coupled to the intermediate node;

a low-to-high transition leg directly coupled to the intermediate node to receive the signal and comprising a first number of transistors;

a high-to-low transition leg directly coupled to the intermediate node to receive the signal and comprising a second number of transistors that is different relative to the first number of transistors; and

an inverter output node coupled to the low-to-high transition leg and to the high-to-low transition leg.

9. The circuit of claim 8, wherein the stacked inverter is operable to provide at the inverter output node an inverted version of an input value at a selected one of the plurality of input nodes.

10. The circuit of claim 8, wherein the first number of transistors is greater than the second number of transistors.

11. The circuit of claim 8, wherein the first number of transistors is less than the second number of transistors.

12. The circuit of claim 8, wherein the first number of transistors comprises p-type transistors, and wherein each p-type transistor includes a respective gate coupled to the inverter input node.

13. The circuit of claim 8, wherein the second number of transistors comprises n-type transistors, and wherein each n-type transistor includes a respective gate coupled to the inverter input node.

14. A circuit, comprising:

a latch;

a transmission gate structure including a plurality of input nodes, an output node operable to output a signal, and a plurality of control nodes coupled to the latch; and

a stacked inverter including;

an inverter input node coupled to the output node;

a low-to-high transition leg directly coupled to the output node to receive the signal and comprising a first number of transistors;

a high-to-low transition leg directly coupled to the output node to receive the signal and comprising a second number of transistors that is different relative to the first number of transistors; and

an inverter output node coupled to the low-to-high transition leg and to the high-to-low transition leg.

15. The circuit of claim 14, wherein the stacked inverter is operable to provide at the inverter output node an inverted version of an input value at a selected one of the plurality of input nodes.

16. The circuit of claim 14, wherein the first number of transistors is greater than the second number of transistors.

17. The circuit of claim 14, wherein the first number of transistors is less than the second number of transistors.

18. The circuit of claim 14, wherein the first number of transistors comprises p-type transistors, and wherein each p-type transistor includes a respective gate coupled to the inverter input node.

19. The circuit of claim 14, wherein the second number of transistors comprises n-type transistors, and wherein each n-type transistor includes a respective gate coupled to the inverter input node.

20. The circuit of claim 14, wherein the transmission gate structure further comprises:

a first transmission gate coupled to a first plurality of the plurality of control nodes and coupled between a first input node of the plurality of input nodes and the output node; and

a second transmission gate coupled to a second plurality of the plurality of control nodes and coupled between a second input node of the plurality of input nodes and the output node.