Techniques for generating clock signals using oscillators

• US 9,531,390 B1
• Filed: 12/15/2015
• Issued: 12/27/2016
• Est. Priority Date: 12/15/2015
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Choi, Dong-Myung, Mendel, David
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US14/969,348
• Time in Patent Office: 378 Days
• Field of Search: 375/376, 375/307, 375/299, 375/295, 455/260, 455/269, 332/159, 332/144, 331/18, 331/2, 331/46, 331/57, 327/156
• US Class Current: 1/1
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers
• CPC Class Codes: H04B 1/16 Circuits

Abstract

An integrated circuit includes first and second data channel circuits and first and second inductor-capacitor (LC) tank oscillator circuits. The first data channel circuit generates a first data signal in response to a first clock signal. The second data channel circuit generates a second data signal in response to a second clock signal. The frequencies of the first and second clock signals are substantially the same. The first LC tank oscillator circuit generates a first periodic signal. The first clock signal is generated in response to the first periodic signal. The second LC tank oscillator circuit generates a second periodic signal. The second clock signal is generated in response to the second periodic signal. The first and second LC tank oscillator circuits generate non-overlapping frequency ranges for the first and second periodic signals.

Claims

1. An integrated circuit comprising:

a first data channel circuit to generate a first data signal in response to a first clock signal;

a second data channel circuit to generate a second data signal in response to a second clock signal, wherein frequencies of the first and second clock signals are substantially the same;

a first inductor-capacitor (LC) tank oscillator circuit to generate a first periodic signal; and

a second LC tank oscillator circuit to generate a second periodic signal, wherein the first and second LC tank oscillator circuits generate non-overlapping frequency ranges for the first and second periodic signals;

a first phase-locked loop circuit comprising a first ring oscillator circuit, wherein the first phase-locked loop circuit generates the first clock signal in response to the first periodic signal; and

a second phase-locked loop circuit comprising a second ring oscillator circuit, wherein the second phase-locked loop circuit generates the second clock signal in response to the second periodic signal.

2. The integrated circuit of claim 1,

wherein the first data channel circuit comprises a first receiver circuit that generates the first data signal in response to the first clock signal, and wherein the second data channel circuit comprises a second receiver circuit that generates the second data signal in response to the second clock signal.

3. The integrated circuit of claim 1 further comprising:

a third phase-locked loop circuit comprising the first LC tank oscillator circuit, wherein the third phase-locked loop circuit generates a third clock signal in response to the first periodic signal, and wherein the first phase-locked loop circuit generates the first clock signal in response to the third clock signal; and

a fourth phase-locked loop circuit comprising the second LC tank oscillator circuit, wherein the fourth phase-locked loop circuit generates a fourth clock signal in response to the second periodic signal, and wherein the second phase-locked loop circuit generates the second clock signal in response to the fourth clock signal.

4. The integrated circuit of claim 3 further comprising:

a plurality of additional data channel circuits, wherein one of the plurality of additional data channel circuits generates a third data signal in response to a fifth clock signal;

a fifth phase-locked loop circuit comprising a third LC tank oscillator circuit that generates a third periodic signal; and

a sixth phase-locked loop circuit comprising a third ring oscillator circuit, wherein the sixth phase-locked loop circuit generates the fifth clock signal in response to the third periodic signal, and wherein the first, second, and third LC tank oscillator circuits generate non-overlapping frequency ranges for the first, second, and third periodic signals.

5. The integrated circuit of claim 3, wherein the third phase-locked loop circuit comprises a first sigma-delta modulator circuit that causes the third phase-locked loop circuit to generate a fractional non-integer frequency in the third clock signal relative to a first input reference clock signal to the third phase-locked loop circuit, and wherein the fourth phase-locked loop circuit comprises a second sigma-delta modulator circuit that causes the fourth phase-locked loop circuit to generate a fractional non-integer frequency in the fourth clock signal relative to a second input reference clock signal to the fourth phase-locked loop circuit.

7. The integrated circuit of claim 1, wherein the first LC tank oscillator circuit causes the frequency range of the first periodic signal to be separated by a frequency value that is greater than zero from the frequency range of the second periodic signal generated by the second LC tank oscillator circuit.

8. The integrated circuit of claim 1, wherein the first data channel circuit comprises a first transmitter circuit that generates the first data signal in response to the first clock signal, and wherein the second data channel circuit comprises a second transmitter circuit that generates the second data signal in response to the second clock signal.

10. The integrated circuit of claim 1, wherein the first data channel circuit is next to the second data channel circuit in the integrated circuit.

6. An integrated circuit comprising:

a first data channel circuit to generate a first data signal in response to a first clock signal;

a second data channel circuit to generate a second data signal in response to a second clock signal, wherein frequencies of the first and second clock signals are substantially the same;

a first inductor-capacitor (LC) tank oscillator circuit to generate a first periodic signal, wherein the first clock signal is generated in response to the first periodic signal; and

a second LC tank oscillator circuit to generate a second periodic signal, wherein the second clock signal is generated in response to the second periodic signal, and wherein the first and second LC tank oscillator circuits generate non-overlapping frequency ranges for the first and second periodic signals,

wherein the first data channel circuit comprises a first receiver circuit that generates the first data signal in response to the first clock signal, and wherein the second data channel circuit comprises a second receiver circuit that generates the second data signal in response to the second clock signal.

9. The integrated circuit of claim 6 further comprising:

a first phase-locked loop circuit comprising the first LC tank oscillator circuit and a first frequency divider circuit that generates the first clock signal in response to the first periodic signal; and

a second phase-locked loop circuit comprising the second LC tank oscillator circuit and a second frequency divider circuit that generates the second clock signal in response to the second periodic signal.

11. An integrated circuit comprising:

a first data channel circuit to generate a first data signal in response to a first clock signal;

a second data channel circuit to generate a second data signal in response to a second clock signal, wherein frequencies of the first and second clock signals are substantially the same;

a first phase-locked loop circuit comprising a first inductor-capacitor (LC) tank oscillator circuit that generates a first periodic signal;

a second phase-locked loop circuit to generate the first clock signal in response to the first periodic signal;

a third phase-locked loop circuit comprising a second LC tank oscillator circuit that generates a second periodic signal; and

a fourth phase-locked loop circuit to generate the second clock signal in response to the second periodic signal, wherein the first and second LC tank oscillator circuits generate non-overlapping frequency ranges for the first and second periodic signals.

12. The integrated circuit of claim 11, wherein the first phase-locked loop circuit further comprises a first frequency divider circuit to generate a third clock signal in response to the first periodic signal, wherein the second phase-locked loop circuit generates the first clock signal in response to the third clock signal, wherein the third phase-locked loop circuit further comprises a second frequency divider circuit to generate a fourth clock signal in response to the second periodic signal, and wherein the fourth phase-locked loop circuit generates the second clock signal in response to the fourth clock signal.

13. The integrated circuit of claim 11, wherein the second phase-locked loop circuit comprises a first ring oscillator circuit, and wherein the fourth phase-locked loop circuit comprises a second ring oscillator circuit.

14. The integrated circuit of claim 11, wherein the first data channel circuit is adjacent to the second data channel circuit in the integrated circuit.

15. The integrated circuit of claim 14, wherein the first data channel circuit comprises a first transmitter circuit that generates the first data signal in response to the first clock signal, and wherein the second data channel circuit comprises a second transmitter circuit that generates the second data signal in response to the second clock signal.

16. A method comprising:

generating a first periodic signal with a first inductor-capacitor (LC) tank oscillator circuit;

generating a first clock signal in response to the first periodic signal with a first phase-locked loop circuit that comprises a first ring oscillator circuit;

generating a first data signal in response to the first clock signal with a first transmitter circuit;

generating a second periodic signal with a second LC tank oscillator circuit, wherein the first and second LC tank oscillator circuits generate non-overlapping frequency ranges in the first and second periodic signals;

generating a second clock signal in response to the second periodic signal with a second phase-locked loop circuit that comprises a second ring oscillator circuit; and

generating a second data signal in response to the second clock signal with a second transmitter circuit, wherein frequencies of the first and second clock signals are substantially the same.

17. The method of claim 16 further comprising:

generating a third clock signal in response to the first periodic signal with a third phase-locked loop circuit that comprises the first LC tank oscillator circuit, and wherein the first phase-locked loop circuit generates the first clock signal in response to the third clock signal; and

generating a fourth clock signal in response to the second periodic signal with a fourth phase-locked loop circuit that comprises the second LC tank oscillator circuit, wherein the second phase-locked loop circuit generates the second clock signal in response to the fourth clock signal.

18. The method of claim 17, wherein the third phase-locked loop circuit comprises a first sigma-delta modulator circuit, and wherein the fourth phase-locked loop circuit comprises a second sigma-delta modulator circuit.

19. The method of claim 16, wherein generating a first clock signal in response to the first periodic signal comprises generating the first clock signal in response to the first periodic signal with a first frequency divider circuit in the first phase-locked loop circuit, and

wherein generating a second clock signal in response to the second periodic signal comprises generating the second clock signal in response to the second periodic signal with a second frequency divider circuit in the second phase-locked loop circuit.

20. A method comprising:

generating a first periodic signal with a first inductor-capacitor (LC) tank oscillator circuit;

generating a first clock signal in response to the first periodic signal with a first phase-locked loop circuit;

generating a first data signal in response to the first clock signal with a first receiver circuit in a first data channel circuit;

generating a second periodic signal with a second LC tank oscillator circuit, wherein the first and second LC tank oscillator circuits generate non-overlapping frequency ranges in the first and second periodic signals;

generating a second clock signal in response to the second periodic signal with a second phase-locked loop circuit; and

generating a second data signal in response to the second clock signal with a second receiver circuit in a second data channel circuit, wherein frequencies of the first and second clock signals are substantially the same.