Method and system for counting data packets

• US 9,531,616 B2
• Filed: 12/07/2010
• Issued: 12/27/2016
• Est. Priority Date: 06/04/2010
• Status: Active Grant

• Current Assignee: ZTE Corporation
• Original Assignee: ZTE Corporation
• Inventors: Yang, Jinmei
• Primary Examiner(s): Rutkowski, Jeffrey M
• Assistant Examiner(s): Li, Ning
• Application Number:
  US13/701,218
• Publication Number:
  US 20130170368A1
• Time in Patent Office: 2,212 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H04L 43/0876 Network utilisation, e.g. volume of load or congestion level
• CPC Class Codes: H04L 43/0888 Throughput

Abstract

The disclosure provides a method for counting data packets, which includes the following steps: counting packet pulse signals when a low bit counter is in a count state, and sending a carry signal when the low bit counter is full; and acquiring data from an address of a Random Access Memory (RAM) corresponding to the low bit counter which sends the carry signal, adding 1 to the acquired data and then writing the added data into the address. The disclosure also provides a system for counting data packets. According to the technical scheme of the disclosure, the occupancy rate of logical resources is reduced while the counting of the data packets in a network is finished at a high speed.

Claims

1. A method for counting data packets, comprising:

counting packet pulse signals when a low bit counter is in a count state, sending a carry signal when the low bit counter is full;

polling all channels and determining a channel in which the low bit counter sends the carry signal, calculating an address of a Random Access Memory (RAM) corresponding to the low bit counter according to a channel number of the channel and a type of the data packets in the channel, and forwarding the calculated RAM address to a state machine;

acquiring, by the state machine, data from the address of the RAM corresponding to the low bit counter adding 1 to the acquired data and writing the added data into the address,

a counting speed for the data packets is increased by combining the low bit counter and the RAM.

2. The method according to claim 1, further comprising:

before the counting packet pulse signals when the low bit counter is in the count state, generating the packet pulse signals according to the data packets.

3. The method according to claim 2, wherein the generating the packet pulse signals according to the data packets comprises:

receiving, by a data channel interface, the data packets transmitted by a data instrument which is connected with the data channel interface, generating various packet pulse signals according to the channel number of the channel and the type of the data packets, and sending the packet pulse signals to the channel.

4. The method according to claim 3, wherein the acquiring data from the address of the RAM corresponding to the low bit counter which sends the carry signal, and adding 1 to the data and writing the data into the address comprises:

receiving, by the state machine, the address of the RAM;

after receiving the address of the RAM, sending, by the state machine, a write enabling pulse signal to the RAM;

when a rising edge of a next clock comes, outputting, by the RAM, the data stored in the address of the RAM to the state machine;

adding, by the state machine, 1 to the data and sending the added data to the RAM to store; and

resetting, by the state machine, the state of the state machine to be a read and write RAM complete state.

5. The method according to claim 2, wherein the acquiring data from the address of the RAM corresponding to the low bit counter which sends the carry signal, and adding 1 to the data and writing the data into the address comprises:

receiving, by the state machine, the address of the RAM;

after receiving the address of the RAM, sending, by the state machine, a write enabling pulse signal to the RAM;

when a rising edge of a next clock comes, outputting, by the RAM, the data stored in the address of the RAM to the state machine;

adding, by the state machine, 1 to the data and sending the added data to the RAM to store; and

resetting, by the state machine, the state of the state machine to be a read and write RAM complete state.

6. The method according to claim 2, further comprising:

after adding 1 to the data and then writing the added data into the address, clearing the carry signal of the low bit counter.

7. The method according to claim 1, further comprising:

resetting data of the low bit counter when the low bit counter is in a reset state;

calculating addresses of RAMs corresponding to all low bit counters in the channel in which the low bit counter is in the reset state, and resetting data in the addresses.

8. The method according to claim 7, wherein the resetting data of the low bit counter when the low bit counter is in the reset state, calculating the addresses of RAMs corresponding to all low bit counters in the channel in which the low bit counter is in the reset state and resetting the data in the addresses comprising:

setting, by the low bit counter, the data of the low bit counter itself to be 0 when the low bit counter is in the reset state;

polling all channels and determining the channel in which the low bit counter is in the reset state, calculating the addresses of the RAMs corresponding to all low bit counters in the channel, and sending the addresses to the state machine;

setting, by the state machine, the data in the addresses to be 0.

9. The method according to claim 8, wherein the acquiring data from the address of the RAM corresponding to the low bit counter which sends the carry signal, and adding 1 to the data and writing the data into the address comprises:

receiving, by the state machine, the address of the RAM;

after receiving the address of the RAM, sending, by the state machine, a write enabling pulse signal to the RAM;

when a rising edge of a next clock comes, outputting, by the RAM, the data stored in the address of the RAM to the state machine;

adding, by the state machine, 1 to the data and sending the added data to the RAM to store; and

resetting, by the state machine, the state of the state machine to be a read and write RAM complete state.

10. The method according to claim 7, wherein the acquiring data from the address of the RAM corresponding to the low bit counter which sends the carry signal, and adding 1 to the data and writing the data into the address comprises:

receiving, by the state machine, the address of the RAM;

after receiving the address of the RAM, sending, by the state machine, a write enabling pulse signal to the RAM;

when a rising edge of a next clock comes, outputting, by the RAM, the data stored in the address of the RAM to the state machine;

adding, by the state machine, 1 to the data and sending the added data to the RAM to store; and

resetting, by the state machine, the state of the state machine to be a read and write RAM complete state.

11. The method according to claim 1, wherein the counting packet pulse signals when the low bit counter is in the count state, and sending the carry signal when the low bit counter is full comprises:

identifying, by the low bit counter in the channel, the packet pulse signals according to a packet header, counting the packet pulse signals, and sending the carry signal used for sending a carry request when the low bit counter is full.

12. The method according to claim 11, wherein the acquiring data from the address of the RAM corresponding to the low bit counter which sends the carry signal, and adding 1 to the data and writing the data into the address comprises:

receiving, by the state machine, the address of the RAM;

after receiving the address of the RAM, sending, by the state machine, a write enabling pulse signal to the RAM;

when a rising edge of a next clock comes, outputting, by the RAM, the data stored in the address of the RAM to the state machine;

adding, by the state machine, 1 to the data and sending the added data to the RAM to store; and

resetting, by the state machine, the state of the state machine to be a read and write RAM complete state.

13. The method according to claim 1, wherein the acquiring data from the address of the RAM corresponding to the low bit counter which sends the carry signal, and adding 1 to the data and writing the data into the address comprises:

receiving, by the state machine, the address of the RAM;

after receiving the address of the RAM, sending, by the state machine, a write enabling pulse signal to the RAM;

when a rising edge of a next clock comes, outputting, by the RAM, the data stored in the address of the RAM to the state machine;

adding, by the state machine, 1 to the data and sending the added data to the RAM to store; and

resetting, by the state machine, the state of the state machine to be a read and write RAM complete state.

14. The method according to claim 1, further comprising:

after adding 1 to the data and then writing the added data into the address, clearing the carry signal of the low bit counter.

15. The method according to claim 14, wherein the clearing the carry signal of the low bit counter comprises:

resetting, by the state machine, a state of the state machine to be a read and write RAM complete state after adding 1 to the data and sending added data to the RAM to store;

after resetting the state of the state machine to be a read and write RAM complete state, triggering a carry clear circuitry to generate a carry clear pulse according to the channel number of the channel and the type of the data packets in the channel, and sending the carry clear pulse to the state machine;

clearing, by the state machine, the carry signal of the low bit counter which generates the carry signal.

16. The method according to claim 1, wherein the acquiring data from the address of the RAM corresponding to the low bit counter which sends the carry signal, and adding 1 to the data and writing the data into the address comprises:

receiving, by the state machine, the address of the RAM;

after receiving the address of the RAM, sending, by the state machine, a write enabling pulse signal to the RAM;

when a rising edge of a next clock comes, outputting, by the RAM, the data stored in the address of the RAM to the state machine;

adding, by the state machine, 1 to the data and sending the added data to the RAM to store; and

resetting, by the state machine, the state of the state machine to be a read and write RAM complete state.

17. A system for counting data packets, comprising:

a low bit counter, a state machine, a Random Access Memory (RAM), a polling algorithm circuitry, and an address arithmetic circuitry, wherein

the low bit counter is configured to count packet pulse signals when the low bit counter is in a count state and to send a carry signal when the low bit counter is full;

the polling algorithm circuitry is configured to poll channels, trigger the address arithmetic circuitry when polling to a channel in which the low bit counter is sending the carry signal;

wherein the address arithmetic circuitry is configured to calculate an address of the RAM corresponding to the low bit counter according to a channel number of the channel and a type of the data packets in the channel and to send the address of the RAM to the state machine;

the state machine is configured to acquire data from the address of the RAM corresponding to the low bit counter which sends the carry signal, to add 1 to the acquired data and to write the added data into the address; and

the RAM is configured to provide the data to the state machine and to store the data written by the state machine,

a counting speed for the data packets is increased by combining the low bit counter and the RAM.

18. The system according to claim 17, further comprising a data channel interface and a carry clear circuitry;

wherein

the data channel interface generates the packet pulse signals according to the data packets;

when the low bit counter is in a reset state, the state machine triggers the carry clear circuitry to generate a carry clear pulse according to the channel number of the channel and the type of the data packets in the channel; and

send the carry clear pulse to the state machine.

19. The system according to claim 18, wherein

the low bit counter resets data of itself when being in the reset state;

the state machine receives the address of the RAM sent from the address arithmetic circuitry, and resets the data in the address of the RAM sent from the address arithmetic circuitry.