Low stress compact device packages

• US 9,533,878 B2
• Filed: 12/11/2014
• Issued: 01/03/2017
• Est. Priority Date: 12/11/2014
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Goida, Thomas M., O'Donnell, Kathleen, Delaus, Michael
• Primary Examiner(s): Ahmed, Selim
• Assistant Examiner(s): CLINTON, EVAN GARRETT
• Application Number:
  US14/567,801
• Publication Number:
  US 20160167951A1
• Time in Patent Office: 754 Days
• US Class Current: 1/1
• CPC Class Codes: B81B 7/0054 between other parts not provided for in B81B7/0048 - B81B7/0051
• CPC Class Codes: B81B 7/0074 3D packaging, i.e. encapsulation containing one or several MEMS devices arranged in planes non-parallel to the mounting board
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/83851 being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06537 Electromagnetic shielding
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/157 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Various low stress compact device packages are disclosed herein. An integrated device package can include a first integrated device die and a second integrated device die. An interposer can be disposed between the first integrated device die and the second integrated device die such that the first integrated device die is mounted to and electrically coupled to a first side of the interposer and the second integrated device die is mounted to and electrically coupled to a second side of the interposer. The first side can be opposite the second side. The interposer can comprise a hole through at least the second side of the interposer. A portion of the second integrated device die can extend into the hole.

Claims

1. An integrated device package comprising:

a first integrated device die;

a second integrated device die;

an interposer disposed between the first integrated device die and the second integrated device die such that the first integrated device die is flip-chip mounted to and electrically coupled to a first side of the interposer and the second integrated device die is flip-chip mounted to and electrically coupled to a second side of the interposer, the first side opposite the second side,

wherein the interposer comprises a hole through at least the second side of the interposer, the first integrated device die including first bond pads connected to the first side of the interposer outside the hole, a first portion of the second integrated device die extending into the hole and a second portion of the second integrated device die disposed vertically and laterally outside the hole on the second side of the interposer, the second portion including second bond pads connected to the second side of the interposer outside the hole.

2. The package of claim 1, wherein the hole comprises a through hole through the interposer.

3. The package of claim 1, wherein the hole comprises a recess formed partially through a thickness of the interposer.

4. The package of claim 1, further comprising an electrical contact disposed on the first side or the second side of the interposer, the electrical contact configured to electrically connect to an external substrate, and wherein the electrical contact has a height that is greater than a thickness of at least one of the first integrated device die and the second integrated device die.

5. The package of claim 4, wherein the electrical contact comprises a plurality of solder balls disposed on the first side of the interposer and wherein the height of the solder balls is greater than the thickness of the first integrated device die.

6. The package of claim 5, wherein the solder balls are disposed around an outer perimeter of the first integrated device die such that a lowermost extent of the solder balls is positioned below a lowermost extent of the first integrated device die.

7. The package of claim 1, wherein the package is not encapsulated with a molding material.

8. The package of claim 1, wherein the second integrated device die comprises a microelectromechanical systems (MEMS) die, and wherein the first portion of the second integrated device die extending into the hole comprises a cap disposed over a MEMS device of the MEMS die.

9. The package of claim 8, wherein the first integrated device die comprises a processor die.

10. The package of claim 1, wherein the second portion of the second integrated device die is wider than the hole.

11. The package of claim 10, further comprising a plurality of electrical contacts disposed between and electrically connecting the second integrated device die and the interposer, the electrical contacts disposed on an outer region of the second portion which surrounds the hole.

12. The package of claim 1, wherein the hole has a major dimension in a lateral direction in a range of 1 mm to 5 mm.

13. The package of claim 1, wherein the first portion of the second integrated device die is spaced from and does not contact the first integrated device die.

14. The package of claim 1, wherein the interposer comprises a through-silicon via (TSV) to provide electrical communication between the first integrated device die and the second integrated device die.

15. The package of claim 1, wherein the first portion of the second integrated device die floats inside a gap defined by the hole such that the first portion does not mechanically connect to the first integrated device die or to the interposer.

16. An integrated device package comprising:

a first integrated device die;

a second integrated device die;

an interposer disposed between the first integrated device die and the second integrated device die such that the first integrated device die is flip chip mounted to and electrically coupled to a first side of the interposer and the second integrated device die is flip chip mounted to and electrically coupled to a second side of the interposer, the first side opposite the second side,

wherein the interposer comprises a hole through at least the second side of the interposer, a portion of the second integrated device die extending into the hole,

wherein the second integrated device die comprises a microelectromechanical systems (MEMS) die, and wherein the portion of the second integrated device die extending into the hole comprises a cap disposed over a MEMS device of the MEMS die,

wherein first bond pads of the first integrated device die connect to the first side of the interposer outside the hole by way of one or more first contacts, and wherein second bond pads of the MEMS die connect to the second side of the interposer outside the hole by way of one or more second contacts.

17. The package of claim 16, wherein the first integrated device die comprises a processor die.

18. A method of manufacturing an integrated device package, the method comprising:

flip chip mounting and electrically coupling a first integrated device die to a first side of an interposer;

inserting a first portion of a second integrated device die into a hole of the interposer;

flip chip mounting and electrically coupling the second integrated device die to a second side of the interposer that is opposite the first side such that a second portion of the second integrated device die is disposed vertically and laterally outside the hole on the second side of the interposer;

connecting first bond pads of the first integrated device die to the first side of the interposer outside the hole; and

connecting second bond pads of the second portion of the second integrated device die to the second side of the interposer outside the hole.

19. The method of claim 18, wherein the first integrated device die comprises a processor die, and wherein the second integrated device die comprises a microelectromechanical systems (MEMS) die.

20. The method of claim 18, further comprising a plurality of electrical contacts disposed on the first side of the interposer, wherein a height of the electrical contacts is greater than a thickness of the first integrated device die.