Method of fabrication of Al/Ge bonding in a wafer packaging environment and a product produced therefrom

• US 9,533,880 B2
• Filed: 09/14/2015
• Issued: 01/03/2017
• Est. Priority Date: 03/18/2005
• Status: Active Grant

• Current Assignee: Invensense Incorporated (TDK Corporation)
• Original Assignee: Invensense Incorporated (TDK Corporation)
• Inventors: Nasiri, Steven S., Flannery, Anthony F. Jr.
• Primary Examiner(s): Blum, David S
• Application Number:
  US14/853,873
• Publication Number:
  US 20160002029A1
• Time in Patent Office: 477 Days
• Field of Search: 438/51, 438/106
• US Class Current: 1/1
• CPC Class Codes: B23K 20/023 Thermo-compression bonding
• CPC Class Codes: B81B 2203/0315 Cavities
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81B 2207/094 Feed-through, via
• CPC Class Codes: B81B 3/0018 Structures acting upon the moving or flexible element for transforming energy into mechanical movement or vice versa, i.e. actuators, sensors, generators
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/035 Soldering
• CPC Class Codes: B81C 2203/038 Bonding techniques not provided for in B81C2203/031 - B81C2203/037
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure
• CPC Class Codes: B81C 3/001 Bonding of two components
• CPC Class Codes: H01L 21/187 by direct bonding

Abstract

A method of bonding of germanium to aluminum between two substrates to create a robust electrical and mechanical contact is disclosed. An aluminum-germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between two substrates; (3) it can be patterned so that this conduction path is localized; (4) the bond can be made with the aluminum that is available as standard foundry CMOS process. This has the significant advantage of allowing for wafer-level bonding or packaging without the addition of any additional process layers to the CMOS wafer.

Claims

1. A method for bonding a first substrate wafer and a second substrate wafer by creating an aluminum/germanium bond, a patterned aluminum layer disposed on the first substrate wafer, a patterned germanium layer disposed on the second substrate wafer, the method comprising:

placing the first substrate wafer in a first chuck;

placing the second substrate wafer in a second chuck;

aligning the first substrate wafer and the second substrate wafer; and

forming a eutectic bond between the patterned germanium layer and the patterned aluminum layer, wherein the eutectic bond is formed by applying a force across the first chuck and the second chuck, and ramping temperature of at least one of the first chuck or the second chuck over a eutectic temperature of the aluminum/germanium bond to a predetermined temperature that is between the eutectic temperature of the aluminum/germanium bond and 450 degrees Celsius (C.).

2. The method of claim 1, wherein one of the first substrate wafer and the second substrate wafer is a cover wafer.

3. The method of claim 1, further comprising:

providing an insulating layer between the second substrate wafer and a portion of the patterned germanium layer.

10. The method of claim 1, wherein the placing the second substrate wafer in the second chuck includes placing the second substrate wafer comprising a microelectromechanical systems (MEMS) structure in the second chuck.

11. The method of claim 1, wherein the placing the first substrate wafer in the first chuck includes placing the first substrate wafer comprising a complementary metal-oxide semiconductor (CMOS) substrate in the first chuck.

4. A method for bonding a first substrate wafer and a second substrate wafer by creating an aluminum/germanium bond, an aluminum layer disposed on the first substrate wafer, a germanium layer disposed on the second substrate wafer, the method comprising:

placing the first substrate wafer in a first chuck;

placing the second substrate wafer in a second chuck;

aligning the first substrate wafer and the second substrate wafer; and

forming a eutectic bond between the germanium layer and the aluminum layer, wherein the eutectic bond is formed by applying a force across the first chuck and the second chuck, and ramping temperature of at least one of the first chuck or the second chuck over a eutectic temperature of the aluminum/germanium bond.

5. The method of claim 4, wherein the ramping of the temperature includes ramping the temperature greater than the eutectic temperature and not exceeding 450 degrees Celsius (C.).

6. The method of claim 4, wherein one of the first substrate wafer and the second substrate wafer is a cover wafer.

7. The method of claim 4, wherein the placing the second substrate wafer in the second chuck includes placing the second substrate wafer comprising a microelectromechanical systems (MEMS) structure in the second chuck.

8. The method of claim 7, wherein the placing the first substrate wafer in the first chuck includes placing the first substrate wafer comprising a complementary metal-oxide semiconductor (CMOS) structure in the first chuck.

9. The method of claim 8, wherein the forming the eutectic bond comprises creating, with the aluminum/germanium bond, at least one of at least one electrical connection or a hermetic seal between first substrate wafer and the second substrate wafer, wherein the hermetic seal forms a partial enclosure of the MEMS structure.

12. The method of claim 4, wherein the forming the eutectic bond comprises creating, with the aluminum/germanium bond, at least one of at least one electrical connection or a hermetic seal between first substrate wafer and the second substrate wafer.