Multi-core microprocessor that dynamically designates one of its processing cores as the bootstrap processor
First Claim
Patent Images
1. A microprocessor, comprising:
- an indicator; and
a plurality of processing cores;
wherein each of the plurality of processing cores is configured to sample the indicator;
wherein when the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor;
wherein when the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor; and
wherein the designated bootstrap processor fetches instructions at an architecturally-defined reset vector and executes the instructions.
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Abstract
A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor.
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Citations
31 Claims
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1. A microprocessor, comprising:
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an indicator; and a plurality of processing cores; wherein each of the plurality of processing cores is configured to sample the indicator; wherein when the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor; wherein when the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor; and wherein the designated bootstrap processor fetches instructions at an architecturally-defined reset vector and executes the instructions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for configuring a multi-core microprocessor, the method comprising:
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sampling an indicator of the microprocessor, wherein the microprocessor comprises a plurality of processing cores; when the indicator indicates a first predetermined value; designating a default one of the plurality of processing cores to be a bootstrap processor; when the indicator indicates a second predetermined value distinct from the first predetermined value; designating one of the plurality of processing cores other than the default processing core to be the bootstrap processor; and wherein the designated bootstrap processor fetches instructions at an architecturally-defined reset vector and executes the instructions. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:
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computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising; first program code for specifying an indicator; and second program code for specifying a plurality of processing cores; wherein each of the plurality of processing cores is configured to sample the indicator; wherein when the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor; wherein when the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor; and wherein the designated bootstrap processor fetches instructions at an architecturally-defined reset vector and executes the instructions. - View Dependent Claims (19)
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20. A microprocessor, comprising:
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an indicator; and a plurality of processing cores; wherein each of the plurality of processing cores is configured to sample the indicator; wherein when the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor; wherein when the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor; and wherein each processing core of the plurality of processing cores is configured to; generate a distinct respective default interrupt controller identifier associated with the processing core; and when the indicator indicates the second predetermined value, modify the associated default respective interrupt controller identifier such that each of the plurality of processing cores has a new distinct respective interrupt controller identifier. - View Dependent Claims (21, 22, 23, 24)
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25. A method for configuring a multi-core microprocessor, the method comprising:
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sampling an indicator of the microprocessor, wherein the microprocessor comprises a plurality of processing cores; when the indicator indicates a first predetermined value; designating a default one of the plurality of processing cores to be a bootstrap processor; when the indicator indicates a second predetermined value distinct from the first predetermined value; designating one of the plurality of processing cores other than the default processing core to be the bootstrap processor; and by each processing core of the plurality of processing cores; generating a distinct respective default interrupt controller identifier associated with the processing core; and when the indicator indicates the second predetermined value, modifying the associated default respective interrupt controller identifier such that each of the plurality of processing cores has a new distinct respective interrupt controller identifier.
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26. A microprocessor, comprising:
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an indicator; and a plurality of processing cores; wherein each of the plurality of processing cores is configured to sample the indicator; wherein when the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor; wherein when the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor; wherein a holding register of the microprocessor comprises the indicator; and wherein the holding register is configured to receive a sensed evaluation of a fuse that is either blown or unblown.
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27. A method for configuring a multi-core microprocessor, the method comprising:
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sampling an indicator of the microprocessor, wherein the microprocessor comprises a plurality of processing cores; when the indicator indicates a first predetermined value; designating a default one of the plurality of processing cores to be a bootstrap processor; and when the indicator indicates a second predetermined value distinct from the first predetermined value; designating one of the plurality of processing cores other than the default processing core to be the bootstrap processor; wherein a holding register of the microprocessor comprises the indicator; and wherein the holding register is configured to receive a sensed evaluation of a fuse that is either blown or unblown.
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28. A microprocessor, comprising:
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an indicator; and a plurality of processing cores; wherein each of the plurality of processing cores is configured to sample the indicator; wherein when the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor; wherein when the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor; wherein a holding register of the microprocessor comprises the indicator; and wherein the holding register is configured to receive a value of the indicator from a boundary scan input.
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29. A method for configuring a multi-core microprocessor, the method comprising:
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sampling an indicator of the microprocessor, wherein the microprocessor comprises a plurality of processing cores; when the indicator indicates a first predetermined value; designating a default one of the plurality of processing cores to be a bootstrap processor; when the indicator indicates a second predetermined value distinct from the first predetermined value; designating one of the plurality of processing cores other than the default processing core to be the bootstrap processor; wherein a holding register of the microprocessor comprises the indicator; and wherein the holding register is configured to receive a value of the indicator from a boundary scan input.
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30. A microprocessor, comprising:
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an indicator; and a plurality of processing cores; wherein each of the plurality of processing cores is configured to sample the indicator; wherein when the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor; wherein when the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor; and wherein the designated bootstrap processor performs a package sleep state handshake protocol for the microprocessor, wherein none of the other plurality of processing cores performs the package sleep state handshake protocol.
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31. A method for configuring a multi-core microprocessor, the method comprising:
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sampling an indicator of the microprocessor, wherein the microprocessor comprises a plurality of processing cores; when the indicator indicates a first predetermined value; designating a default one of the plurality of processing cores to be a bootstrap processor; when the indicator indicates a second predetermined value distinct from the first predetermined value; designating one of the plurality of processing cores other than the default processing core to be the bootstrap processor; and wherein the designated bootstrap processor performs a package sleep state handshake protocol for the microprocessor, wherein none of the other plurality of processing cores performs the package sleep state handshake protocol.
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Specification