Atomic operations in PCI express

• US 9,535,838 B2
• Filed: 11/30/2012
• Issued: 01/03/2017
• Est. Priority Date: 11/02/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ajanovic, Jasmin, Wagh, Mahesh, Sethi, Prashant, Das Sharma, Debendra, Harriman, David J., Rosenbluth, Mark B., Bhatt, Ajay V., Barry, Peter, Rodgers, Scott Dion, Vasudevan, Anil, Muthrasanallur, Sridhar, Akiyama, James, Blankenship, Robert G., Falik, Ohad, Mendelson, Avi, Pardo, Ilan, Tamari, Eran, Weissmann, Eliezer, Shamia, Doron
• Primary Examiner(s): Martinez, David E
• Application Number:
  US13/691,106
• Publication Number:
  US 20130111086A1
• Time in Patent Office: 1,495 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4265 on a point to point bus G06F13/4247, G06F13/4282 take precedence
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Claims

1. An apparatus comprising:

an I/O element to;

receive a transaction layer packet of a transaction from a device over an interconnect;

identify, from a header of the packet, an atomic operation request on a data unit, wherein the header comprises a type field to indicate an atomic operation type of the atomic operation request, a tag field, a requester identifier (ID) field, and an address field; and

service the atomic operation request.

2. The apparatus of claim 1, wherein the interconnect comprises at least one of a Peripheral Component Interconnect Express (PCIe)-compliant interconnect, a physical layer to support PCIe protocols, a Common Systems Interconnect (CSI)-compliant interconnect, and a physical layer to support a layered communication protocol.

3. The apparatus of claim 1, wherein the I/O element includes a layered protocol stack including a transaction layer, a link layer, and a physical layer.

4. The apparatus of claim 1, wherein the apparatus comprises a root controller.

5. The apparatus of claim 1, wherein the I/O element is to send a completion message in response to the received packet based at least in part on servicing of the atomic operation request.

6. The apparatus of claim 5, wherein the completion message identifies a value of the particular data unit prior to servicing of the atomic operation request.

7. The apparatus of claim 1, wherein the atomic operation request is for a read-modify-write atomic operation on the particular data unit.

8. The apparatus of claim 7, wherein the atomic operation includes performance of two'"'"'s complement addition on a value of the particular data unit.

9. The apparatus of claim 7, wherein the atomic operation includes performance of a swap on a value of the particular data unit.

10. The appearance of claim 7, wherein the atomic operation includes performance of a conditional swap on a value of the particular data unit.

11. The apparatus of claim 1, wherein the atomic operation type is one of a group including:

a) two'"'"'s compliment add,

b) swap, and

c) test and swap.

12. The apparatus of claim 1, wherein the address field identifies address information of the particular data unit.

13. An apparatus comprising:

logic to;

receive a packet including a packet header, wherein the packet header comprises a type field, a tag field, a requester identifier (ID) field, and an address field, wherein the packet is received over a Peripheral Component Interconnect Express (PCIe)-compliant interconnect and a value of the type field indicates whether the packet corresponds to a request for an atomic operation; and

identify that the packet corresponds to a particular type of atomic operation request based at least in part on the value of the type field; and

service the particular type of atomic operation request.

14. The apparatus of claim 13, wherein the type field identifies a type of requested operation.

15. The apparatus of claim 14, wherein the type is one of a group comprising:

a) a bit set operation;

b) a bit clear operation;

c) two'"'"'s complement add operation;

d) add operation;

e) swap operation; and

f) test and swap operation.

16. A method comprising:

receiving a transaction layer packet from a device over a PCIe-compliant interconnect, wherein the packet comprises a packet header comprising a type field, a tag field, a requester identifier (ID) field, and an address field;

decoding the packet header to identify an atomic operation request on a data unit;

identifying, from a type field of the packet header, an atomic operation type of the atomic operation request; and

servicing the atomic operation request.

17. The method of claim 16, wherein servicing the atomic operation request includes:

reading a first value of the data unit;

writing a second, new value to the data unit; and

returning the first value of the data unit in a response to the device.

18. The method of claim 17, wherein the response includes a completion message sent to the device indicating that the atomic operation request has been serviced.

19. A system comprising:

a first I/O device;

a memory element; and

a second I/O device communicatively coupled to the first I/O device, wherein the second I/O device is to;

receive a packet from the first I/O device in a transaction over a PCIe-compliant interconnect, wherein the packet comprises a packet header and a payload, and the packet header comprises a type field, a tag field, a requester identifier (ID) field, and an address field;

decode the packet header to identify an atomic operation request on a data unit stored on the memory element and identify, from the type field of the packet header, an atomic operation type of the atomic operation request;

service the atomic operation request; and

return a response to the first I/O device based on servicing of the atomic operation request.

20. The system of claim 19, wherein the first I/O device is to:

generate the atomic operation request, wherein the atomic operation request identifies one of a plurality of available atomic operation types; and

receive the response from the second I/O device, wherein the response includes identification of a value of the data unit prior to servicing of the atomic operation request.

21. The system of claim 19, wherein the memory element includes host memory of the second I/O device.

22. The system of claim 21, wherein the first I/O device is included in a root controller and the root controller and second I/O device are communicatively coupled using the interconnect.

23. The system of claim 22, wherein the root controller is communicatively coupled over a PCIe-compliant interconnect to a plurality of endpoint devices including the second I/O device.

24. The system of claim 23, wherein the root controller is coupled to at least one microcontroller.

25. The system of claim 19, wherein the memory element comprises shared memory of the system.