Method and system of change evaluation of an electronic design for verification confirmation

• US 9,536,028 B2
• Filed: 06/30/2015
• Issued: 01/03/2017
• Est. Priority Date: 06/27/2013
• Status: Active Grant

• Current Assignee: Zipalog, Inc.
• Original Assignee: Zipalog, Inc.
• Inventors: Krasnicki, Michael, Deng, Yue
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US14/788,091
• Publication Number:
  US 20150302125A1
• Time in Patent Office: 553 Days
• Field of Search: 716100-101, 716106-107
• US Class Current: 1/1
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/36 Circuit design at the analogue level
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/38 Circuit design at the mixed level of analogue and digital signals
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A computer implemented method and system of change evaluation of an electronic design for verification confirmation. The method has the steps of receiving the electronic design comprised a subcomponent, employing a banked signature of data representative of the subcomponent, receiving a review request of the subcomponent, generating a current signature of the data representative of the subcomponent and determining a difference of the current signature and the banked signature.

Claims

1. A computer implemented method of change evaluation of an electronic design file for design verification confirmation prior to fabrication of an electronic circuit defined by the electronic design file, comprising the steps of:

receiving, at a processor, a representation of said electronic design file defining the electronic circuit, the representation comprised at least in part of a hierarchy of the electronic circuit having at least one subcomponent of the electronic circuit, wherein the electronic design file defines a functional level electronic design of the electronic circuit;

receiving, at the processor, along with said representation of said electronic design file, at least one test harness model to test said at least one subcomponent of the electronic circuit defined by the electronic design file;

storing, at the processor, a banked signature of data representative of said at least one subcomponent of the electronic circuit defined by the electronic design file and said at least one test harness model associated with the electronic design file;

receiving, at the processor, at least one review request of said at least one subcomponent of the electronic circuit defined by the electronic design file and said at least one test harness model associated with the electronic design file;

generating, at the processor, a current signature of data representative of said at least one subcomponent of the electronic circuit defined by the electronic design file and said at least one test harness model associated with the electronic design file in response to said at least one review request;

determining, at the processor, a difference based at least in part upon said current signature associated with the electronic design file and said banked signature associated with the electronic design file; and

evaluating, at the processor, an equivalence of said at least one subcomponent of the electronic circuit defined by the electronic design file and said at least one reviewed subcomponent of the electronic circuit defined by the electronic design file.

2. The computer implemented method of change evaluation of the functional level electronic design for verification confirmation of claim 1, wherein said at least one test harness model associated with the electronic design file is analog.

3. The computer implemented method of change evaluation of the functional level electronic design for verification confirmation of claim 1, wherein said at least one test harness model associated with the electronic design file is mixed signal.

4. The computer implemented method of change evaluation of the functional level electronic design for verification confirmation of claim 1, wherein said at least one test harness model associated with the electronic design file is digital.

5. The computer implemented method of change evaluation of the functional level electronic design for verification confirmation of claim 1, wherein said banked signature associated with the electronic design file is at least one of a cryptographic signature, a timestamp and a bit copy.

6. The computer implemented method of change evaluation of the functional level electronic design for verification confirmation of claim 1, further comprising at least one of determining a verification history of said electronic design and receiving said verification history of said electronic design.

7. The computer implemented method of change evaluation of the functional level electronic design for verification confirmation of claim 1, further comprising receiving at least one modification of said at least one subcomponent of the electronic circuit defined by the electronic design file.

8. A computer-based system of confirming verification based on change evaluation of an electronic design file that has been subject to modification, prior to fabrication of an electronic circuit defined by the electronic design file, comprising:

a computer processor to execute a set of program code instructions;

a memory to hold a banked signature associated with the electronic design file and said program code instructions, in which said program code instructions comprises program code to;

receive, at the processor, a representation of said electronic design file comprised at least in part of a hierarchy of the electronic circuit having at least one subcomponent of the electronic circuit, wherein the electronic design file defines a functional level electronic design of the electronic circuit;

receive, at the processor, along with said representation of said electronic design file, at least one test harness model to test said at least one subcomponent of the electronic circuit defined by the electronic design file;

receive, at the processor, at least one review request of said at least one subcomponent of the electronic circuit defined by the electronic design file and said at least one test harness model associated with the electronic design file;

store, at the processor, a banked signature associated with the electronic design file of data representative of said at least one subcomponent of the electronic circuit defined by the electronic design file and said at least one test harness model associated with the electronic design file;

generating, at the processor, a current signature associated with the electronic design file of data representative of said at least one subcomponent of the electronic circuit defined by the electronic design file and said at least one test harness model associated with the electronic design file in response to said at least one review request;

determine, at the processor, a difference based at least in part upon said current signature associated with the electronic design file and said banked signature associated with the electronic design file; and

evaluating, at the processor, an equivalence of said at least one subcomponent of the electronic circuit defined by the electronic design file and said at least one reviewed subcomponent of the electronic circuit defined by the electronic design file.

9. The system of claim 8, wherein said at least one test harness model associated with the electronic design file is analog.

10. The system of claim 8, wherein said at least one test harness model associated with the electronic design file is mixed signal.

11. The system of claim 8, wherein said at least one test harness associated with the electronic design file model is digital.

12. The system of claim 8, wherein said banked signature associated with the electronic design file is at least a cryptographic signature.

13. The system of claim 8, wherein said banked signature associated with the electronic design file is at least a timestamp.

14. The system of claim 8, wherein said banked signature associated with the electronic design file is at least a bit copy.

15. A non-transitory computer readable storage medium configured to store instructions that when executed causes at least one processor to perform:

receiving, at the processor, a representation of an electronic design file comprised at least in part of a hierarchy of an electronic circuit having at least one subcomponent of the electronic circuit, wherein the electronic design file defines a functional level electronic design of the electronic circuit;

receiving, at the processor, along with said representation of said electronic design file, at least one test harness model to test said at least one subcomponent of the electronic circuit defined by the electronic design file;

retrieving, at the processor, a banked signature of data representative of said at least one subcomponent of the electronic circuit defined by the electronic design file and said at least one test harness model associated with the electronic design file;

receiving, at the processor, at least one review request of said at least one subcomponent of the electronic circuit defined by the electronic design file and said at least one test harness model associated with the electronic design file;

generating, at the processor, a current signature of data representative of said at least one subcomponent of the electronic circuit and said at least one test harness model associated with the electronic design file in response to said at least one review request;

determining, at the processor, a difference based at least in part upon said current signature associated with the electronic design file and said banked signature associated with the electronic design file; and

evaluating, at the processor, an equivalence of said at least one subcomponent of the electronic circuit defined by the electronic design file and said at least one reviewed subcomponent of the electronic circuit defined by the electronic design file.

16. The non-transitory computer readable storage medium of claim 15, wherein said functional level electronic design is analog.

17. The non-transitory, computer readable storage medium of claim 15, wherein said functional level electronic design is mixed signal.

18. The non-transitory, computer readable storage medium of claim 15, wherein said banked signature associated with the electronic design file is a cryptographic signature.

19. The non-transitory, computer readable storage medium of claim 15, wherein said banked signature associated with the electronic design file is a timestamp.

20. The non-transitory, computer readable storage medium of claim 15, wherein said banked signature associated with the electronic design file is a bit copy.