Method and system of layout placement based on multilayer gridlines

• US 9,536,032 B2
• Filed: 11/26/2014
• Issued: 01/03/2017
• Est. Priority Date: 05/02/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chiang, Ting-Wei, Tien, Li-Chun, Zhuang, Hui-Zhong, Jiang, Zhe-Wei
• Primary Examiner(s): Levin, Naum B
• Application Number:
  US14/554,958
• Publication Number:
  US 20160147926A1
• Time in Patent Office: 769 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H03K 19/02 using specified components H03K19/0005 - H03K19/0021, H03K19/003 - H03K19/0175 take precedence

Abstract

A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes identifying a line pattern of a first set of grid lines with respect to a second set of grid lines within a region of the layout design; and placing a k-th standard cell layout of the K standard cell layouts at the region of the layout design if the line pattern is determined to match a k-th predetermined line pattern of K predetermined line patterns. K is an integer equal to or greater than two, and k is an order index ranging from 1 to K. The region of the layout design is sized to fit one of K different standard cell layouts corresponding to a same standard cell functionality.

Claims

1. A method of forming a layout design for fabricating an integrated circuit, the method comprising:

identifying a line pattern of a first set of grid lines with respect to a second set of grid lines within a region of the layout design, the region of the layout design being sized to fit one of K different standard cell layouts corresponding to a same standard cell functionality, K being an integer equal to or greater than two, the first set of grid lines extending along a first direction and corresponding to placement of a first set of layout patterns of a first layout layer of the layout design, the second set of grid lines extending along the first direction and corresponding to placement of a second set of layout patterns of a second layout layer of the layout design, the first set of grid lines having a first line pitch, and the second set of grid lines having a second line pitch different from the first line pitch,

wherein the line pattern includes a layout pattern aligned with a grid line of the first set of grid lines overlapping a layout pattern aligned with a grid line of the second set of grid lines; and

placing a k-th standard cell layout of the K standard cell layouts at the region of the layout design if the line pattern is determined to match a k-th predetermined line pattern of K predetermined line patterns, k being an order index ranging from 1 to K, and

at least one of the above operations being performed by a hardware processor.

2. The method of claim 1, wherein

a ratio of the first line pitch to the second line pitch is M:

N, M and N being positive integers;

two cell boundaries of the k-th standard cell layout overlap two corresponding grid lines of the first set of grid lines; and

3. The method of claim 1, wherein the placing the k-th standard cell layout of the K standard cell layouts is performed in a manner such that two cell boundaries of the k-th standard cell layout overlap two corresponding grid lines of the first set of grid lines.

4. The method of claim 1, wherein the first line pitch is greater than the second line pitch.

5. The method of claim 1, wherein the K predetermined line patterns comprise:

a same placement for the first set of grid lines; and

K different placements for the second set of grid lines.

6. The method of claim 1, wherein

the first layout layer corresponds to fabricating a first component layer of the integrated circuit;

the second layout layer corresponds to fabricating a second component layer of the integrated circuit; and

the first component layer and the second component layer each correspond to a different one of the following component layers of the integrated circuit;

a gate structure layer;

a first conductive layer over the gate structure layer; and

a second conductive layer over the first conductive layer.

7. The method of claim 1, wherein

the first layout layer corresponds to fabricating a first component layer of the integrated circuit;

the second layout layer corresponds to fabricating a second component layer of the integrated circuit; and

the first component layer and the second component layer each correspond to a different one of the following component layers of the integrated circuit;

a fin structure layer for FinFETs;

a first conductive layer over the fin structure layer; and

a second conductive layer over the first conductive layer.

8. A method of forming a layout design for fabricating an integrated circuit, the method comprising:

identifying a line pattern of a first set of grid lines with respect to a second set of grid lines within a region of the layout design, the first set of grid lines extending along a first direction and corresponding to placement of a first set of layout patterns of a first layout layer of the layout design, the second set of grid lines extending along the first direction and corresponding to placement of a second set of layout patterns of a second layout layer of the layout design, the first set of grid lines having a first line pitch, and the second set of grid lines having a second line pitch different from the first line pitch; and

placing a plurality of standard cell layouts at the region of the layout design, the plurality of standard cell layouts having different cell widths measurable along a second direction or having different cell heights measurable along the second direction, wherein

a ratio of the first line pitch to the second line pitch is M;

N, M and N being positive integers;

the cell widths or the cell heights of the plurality of standard cell layouts are integer multiples of R;

9. The method of claim 8, wherein the first pitch is greater than the second pitch.

10. The method of claim 8, wherein

the first layout layer corresponds to fabricating a first component layer of the integrated circuit;

the second layout layer corresponds to fabricating a second component layer of the integrated circuit; and

the first component layer and the second component layer each correspond to a different one of the following component layers of the integrated circuit;

a gate structure layer;

a first conductive layer over the gate structure layer; and

a second conductive layer over the first conductive layer.

11. The method of claim 8, wherein

the first layout layer corresponds to fabricating a first component layer of the integrated circuit;

the second layout layer corresponds to fabricating a second component layer of the integrated circuit; and

the first component layer and the second component layer each correspond to a different one of the following component layers of the integrated circuit;

a fin structure layer for FinFETs;

a first conductive layer over the fin structure layer; and

a second conductive layer over the first conductive layer.

12. A system of forming a layout design, comprising:

a non-transitory storage medium encoded with a set of instructions; and

a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute the set of instruction, the set of instruction being configured to cause the processor to;

identify a line pattern of a first set of grid lines with respect to a second set of grid lines within a region of a layout design, the region of the layout design being sized to fit one of K different standard cell layouts corresponding to a same standard cell functionality, K being an integer equal to or greater than two, the first set of grid lines extending along a first direction and corresponding to placement of a first set of layout patterns of a first layout layer of the layout design, the second set of grid lines extending along the first direction and corresponding to placement of a second set of layout patterns of a second layout layer of the layout design, the first set of grid lines having a first line pitch, and the second set of grid lines having a second line pitch different from the first line pitch,

wherein the line pattern includes a layout pattern aligned with a grid line of the first set of grid lines overlapping a layout pattern aligned with a grid line of the second set of grid lines at a location other than a cell boundary; and

place a k-th standard cell layout of the K standard cell layouts at the region of the layout design if the line pattern is determined to match a k-th predetermined line pattern of K predetermined line patterns, k being an order index ranging from 1 to K.

13. The system of claim 12, wherein

a ratio of the first line pitch to the second line pitch is M:

N, M and N being positive integers;

two cell boundaries of the k-th standard cell layout overlap two corresponding grid lines of the first set of grid lines; and

14. The system of claim 12, wherein the placing the k-th standard cell layout of the K standard cell layouts is performed in a manner such that two cell boundaries of the k-th standard cell layout overlap two corresponding grid lines of the first set of grid lines.

15. The system of claim 12, wherein the K predetermined line patterns comprise:

a same placement for the first set of grid lines; and

K different placements for the second set of grid lines.

16. The system of claim 12, wherein

the first layout layer corresponds to fabricating a first component layer of the integrated circuit;

the second layout layer corresponds to fabricating a second component layer of the integrated circuit; and

the first component layer and the second component layer each correspond to a different one of the following component layers of the integrated circuit;

a gate structure layer;

a first conductive layer over the gate structure layer; and

a second conductive layer over the first conductive layer.

17. The system of claim 12, wherein

the first layout layer corresponds to fabricating a first component layer of the integrated circuit;

the second layout layer corresponds to fabricating a second component layer of the integrated circuit; and

the first component layer and the second component layer each correspond to a different one of the following component layers of the integrated circuit;

a fin structure layer for FinFETs;

a first conductive layer over the fin structure layer; and

a second conductive layer over the first conductive layer.

18. A system of forming a layout design, comprising:

a non-transitory storage medium encoded with a set of instructions; and

a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute the set of instruction, the set of instruction being configured to cause the processor to;

identify a line pattern of a first set of grid lines with respect to a second set of grid lines within a region of the layout design, the first set of grid lines extending along a first direction and corresponding to placement of a first set of layout patterns of a first layout layer of the layout design, the second set of grid lines extending along the first direction and corresponding to placement of a second set of layout patterns of a second layout layer of the layout design, the first set of grid lines having a first line pitch, and the second set of grid lines having a second line pitch different from the first line pitch; and

place a plurality of standard cell layouts at the region of the layout design, the plurality of standard cell layouts having different cell widths measurable along a second direction or having different cell heights measurable along the second direction, wherein

a ratio of the first line pitch to the second line pitch is M;

N, M and N being positive integers;

the cell widths or the cell heights of the plurality of standard cell layouts are integer multiples of R;

19. The system of claim 18, wherein

the first layout layer corresponds to fabricating a first component layer of the integrated circuit;

the second layout layer corresponds to fabricating a second component layer of the integrated circuit; and

the first component layer and the second component layer each correspond to a different one of the following component layers of the integrated circuit;

a gate structure layer;

a first conductive layer over the gate structure layer; and

a second conductive layer over the first conductive layer.

20. The system of claim 18, wherein

the first layout layer corresponds to fabricating a first component layer of the integrated circuit;

the second layout layer corresponds to fabricating a second component layer of the integrated circuit; and

the first component layer and the second component layer each correspond to a different one of the following component layers of the integrated circuit;

a fin structure layer for FinFETs;

a first conductive layer over the fin structure layer; and

a second conductive layer over the first conductive layer.