Power source for memory circuitry

• US 9,536,575 B2
• Filed: 10/07/2015
• Issued: 01/03/2017
• Est. Priority Date: 01/14/2015
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Peng, Wu-Chin, Lee, Chun-Yi, Chen, Ken-Hui, Chang, Kuen-Long, Hung, Chun Hsiung
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US14/877,692
• Publication Number:
  US 20160203845A1
• Time in Patent Office: 454 Days
• Field of Search: 365/226, 365/203
• US Class Current: 1/1
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

An integrated circuit comprises a power supply input pin for receiving an off-chip supply voltage which can have a variable current, an on-chip power source to be powered by the off-chip supply voltage and which can provide a regulated current, a set of one or more circuits to be powered by at least one of the off-chip supply voltage and the on-chip power source, a configuration memory storing a set of one or more memory settings that indicate whether a circuit of said set of one or more circuits is powered by the on-chip power source, and control circuitry responsive to the at least one memory setting to control whether said circuit of said set of one or more circuits is powered by the on-chip power source.

Claims

1. An integrated circuit comprising:

a power supply input pin for receiving an off-chip supply voltage;

an on-chip power source to be powered by the off-chip supply voltage;

a set of one or more circuits;

a configuration memory storing a set of one or more memory settings that indicates whether each member of the set of one or more circuits is powered by the on-chip power source or by the off-chip supply voltage; and

control circuitry, responsive to the set of one or more memory settings, controlling whether each member of the set of one or more circuits is powered by the on-chip power source or by the off-chip supply voltage.

2. The integrated circuit of claim 1, wherein the set of one or more circuits includes a charge pump driven by a multi-phase clock signal, the multi-phase clock signal having a voltage-versus-time slope determined by a regulated current.

3. The integrated circuit of claim 1, wherein:

the set of one or more circuits includes components of a charge pump, the components of the charge pump including a plurality of serially coupled charge pump stages arranged to pump charge from a first stage to a last stage of the plurality; and

the charge pump stages of the plurality include an input node, an output node, a pass transistor electrically coupling the input node and the output node, a first boost capacitor coupled to the output node, and a second boost capacitor coupled to a gate of the pass transistor.

4. The integrated circuit of claim 1, wherein:

the set of one or more circuits includes components of a charge pump, the components of the charge pump including a plurality of serially coupled charge pump stages arranged to pump charge from a first stage to a last stage of the plurality;

a particular stage of the plurality of serially coupled charge pump stages includes;

a first transistor selectively electrically coupling an input node of the particular stage and an output node of the particular stage; and

a second transistor selectively electrically coupling the input node and a gate of the first transistor;

the particular stage is in a well surrounded by a plurality of well contacts; and

the input node is defined by a first region in the well, the output node is defined by a second region in the well, the first region and the second region are on opposite sides of the gate of the first transistor, the first region having a first distance from a nearest well contact of the plurality of well contacts averaged along a first perimeter of the first region, the second region having a second distance from another nearest well contact of the plurality of well contacts averaged along a second perimeter of the first region, the second distance shorter than the first distance.

5. The integrated circuit of claim 1, wherein:

the set of one or more circuits includes components of a charge pump, the components of the charge pump including a plurality of serially coupled charge pump stages arranged to pump charge from a first stage to a last stage of the plurality;

a particular stage of the plurality of serially coupled charge pump stages includes a first transistor selectively electrically coupling an input node of the particular stage and an output node of the particular stage, and a second transistor selectively electrically coupling the input node and a gate of the first transistor;

the particular stage is in a well surrounded by a plurality of well contacts; and

the input node is defined by a first region in the well, the output node is defined by a plurality of second regions in the well, and the first region is between the plurality of second regions.

6. The integrated circuit of claim 1, wherein:

the on-chip power source includes a plurality of parallel current sources; and

the integrated circuit includes an additional set of one or more memory settings that indicates whether a particular parallel current source of the plurality of parallel current sources provides current that is included in a regulated current.

7. The integrated circuit of claim 1, wherein:

the on-chip power source includes;

a reference current source; and

a plurality of transistors having at least two different widths;

at least a first transistor of the plurality of transistors is in series with the reference current source; and

wherein at least a second transistor of the plurality of transistors provides an output current determined by a ratio of the at least two different widths of at least the first and the second transistors of the plurality of transistors.

8. The integrated circuit of claim 7, wherein the on-chip power source includes an operational amplifier in a loop from a gate of at least the first transistor of the plurality of transistors to the reference current source.

9. The integrated circuit of claim 1, wherein the on-chip power source has a nominal output voltage that is independent of the off-chip supply voltage.

10. The integrated circuit of claim 1, wherein the set of one or more circuits includes a capacitive boosting circuit.

11. The integrated circuit of claim 1, wherein the set of one or more circuits includes an output driver.

12. The integrated circuit of claim 1, wherein the set of one or more circuits includes a clock circuit.

13. The integrated circuit of claim 1, further comprising:

a semiconductor body having a particular conductivity type;

a first well in the semiconductor body having the particular conductivity type;

a second well in the semiconductor body surrounding the first well and having an opposite conductivity type relative to the particular conductivity type;

a plurality of transistors arranged to pump a voltage level from a first transistor to a last transistor in response to one or more clock signals, the last transistor having a voltage level substantially higher than, or negative relative to, a power supply voltage coupled to the plurality of transistors; and

at least one of the plurality of transistors having a source and a drain region of the opposite conductivity type formed in the first well, the first well, the second well and the drain region being coupled to a common potential,

wherein the set of one or more circuits includes the plurality of transistors.

14. An integrated circuit comprising:

a power supply input pin for receiving an off-chip supply voltage;

an on-chip power source to be powered by the off-chip supply voltage;

a set of one or more circuits to be powered by at least one of the off-chip supply voltage and the on-chip power source;

a configuration memory storing a set of one or more memory settings that indicates whether at least one circuit of the set of one or more circuits is powered by the on-chip power source; and

control circuitry, responsive to the set of one or more memory settings, controlling whether the at least one circuit is powered by the on-chip power source, wherein;

the set of one or more circuits includes components of a charge pump, the components of the charge pump including a plurality of serially coupled charge pump stages arranged to pump charge from a first stage to a last stage of the plurality;

the charge pump stages of the plurality including an input node, an output node, a pass transistor electrically coupling the input node and the output node, a first boost capacitor coupled to the output node, and a second boost capacitor coupled to a gate of the pass transistor; and

the memory settings indicate whether at least one of;

(i) the first boost capacitors, (ii) the second boost capacitors, and (iii) the input node of a first stage are powered by the on-chip power source.

15. A method comprising:

accessing, from an integrated circuit, a set of one or more memory settings that indicates whether each member of a set of one or more circuits is powered by an on-chip power source or by an off-chip supply voltage, the on-chip power source powered by the off-chip supply voltage via a power supply input pin; and

responsive to the set of one or more memory settings, controlling whether each member of the set of one or more circuits is powered by the on-chip power source or by the off-chip supply voltage.

16. The method of claim 15, wherein:

the memory settings indicate whether at least one of;

(i) first boost capacitors, (ii) second boost capacitors, and (iii) an input node of a first stage are powered by the on-chip power source or by the off-chip supply voltage;

the set of one or more circuits includes components of a charge pump, the components of the charge pump including a plurality of serially coupled charge pump stages arranged to pump charge from the first stage to a last stage of the plurality; and

the charge pump stages of the plurality include the input node, an output node, a pass transistor electrically coupling the input node and the output node, the first boost capacitor coupled to the output node, and the second boost capacitor coupled to a gate of the pass transistor.

17. The method of claim 15, wherein:

the set of one or more circuits includes components of a charge pump, the components of the charge pump including a plurality of serially coupled charge pump stages arranged to pump charge from a first stage to a last stage of the plurality;

a particular stage of the plurality of serially coupled charge pump stages includes;

a first transistor selectively electrically coupling an input node of the particular stage and an output node of the particular stage; and

a second transistor selectively electrically coupling the input node and a gate of the first transistor;

the particular stage is in a well surrounded by a plurality of well contacts; and

the input node is defined by a first region in the well, the output node is defined by a second region in the well, the first region and the second region on opposite sides of the gate of the first transistor, the first region having a first distance from a nearest well contact of the plurality of well contacts averaged along a first perimeter of the first region, the second region having a second distance from another nearest well contact of the plurality of well contacts averaged along a second perimeter of the first region, the first distance shorter than the second distance.

18. The method of claim 15, wherein:

the set of one or more circuits includes components of a charge pump, the components of the charge pump including a plurality of serially coupled charge pump stages arranged to pump charge from a first stage to a last stage of the plurality;

a particular stage of the plurality of serially coupled charge pump stages includes a first transistor selectively electrically coupling an input node of the particular stage and an output node of the particular stage, and a second transistor selectively electrically coupling the input node and a gate of the first transistor;

the particular stage is in a well surrounded by a plurality of well contacts; and

the input node is defined by a first region in the well, the output node is defined by a plurality of second regions in the well, and the first region is between the plurality of second regions.

19. The method of claim 15, wherein:

the on-chip power source includes a plurality of parallel current sources; and

the integrated circuit includes an additional set of one or more memory settings that indicates whether a particular parallel current source of the plurality of parallel current sources provides current that is included in a regulated current.

20. The method of claim 15, wherein:

the on-chip power source includes;

a reference current source; and

a plurality of transistors having at least two different widths;

at least a first transistor of the plurality of transistors is in series with the reference current source; and

at least a second transistor of the plurality of transistors provides an output current determined by a ratio of the at least two different widths of at least the first and the second transistors of the plurality of transistors.