Staggered DLL clocking on N-Detect QED to minimize clock command and delay path
First Claim
1. An apparatus, comprising:
- a timing circuit configured to receive an external clock signal and provide an internal clock signal;
a clock stagger circuit configured to receive the internal clock signal and provide at least one delayed internal clock signal; and
a command decode and delay path configured to receive a command, and further configured to delay the command and provide a delayed command, wherein the command decode and delay path includes a shift circuit coupled to the timing circuit and to the clock stagger circuit, and configured to receive the internal clock signal from the timing circuit and to receive the at least one delayed internal clock signal from the clock stagger circuit, the shift circuit further configured to capture the delayed command according to an external clock domain and provide the delayed command according to an internal clock domain based on one or both of the internal clock signal and the delayed internal clock signal.
8 Assignments
0 Petitions
Accused Products
Abstract
Apparatuses and methods are described for meeting timing and latency requirements using staggered clocking within the command path. In one example, an apparatus is disclosed that includes a timing circuit configured to provide an internal clock signal; a clock stagger circuit configured to receive the internal clock signal from the timing circuit and to generate at least one delayed internal clock signal; and a shift circuit arranged in a command decode and delay path of a command signal, coupled to the timing circuit and to the clock stagger circuit, and configured to capture the command from an external clock domain into an internal clock domain based on one or both of the internal clock signal and the delayed internal clock signal
-
Citations
20 Claims
-
1. An apparatus, comprising:
-
a timing circuit configured to receive an external clock signal and provide an internal clock signal; a clock stagger circuit configured to receive the internal clock signal and provide at least one delayed internal clock signal; and a command decode and delay path configured to receive a command, and further configured to delay the command and provide a delayed command, wherein the command decode and delay path includes a shift circuit coupled to the timing circuit and to the clock stagger circuit, and configured to receive the internal clock signal from the timing circuit and to receive the at least one delayed internal clock signal from the clock stagger circuit, the shift circuit further configured to capture the delayed command according to an external clock domain and provide the delayed command according to an internal clock domain based on one or both of the internal clock signal and the delayed internal clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A method of controlling signals in a memory device, comprising:
-
providing an internal clock signal from a delay locked loop; receiving the internal clock signal at a clock stagger circuit; generating at least one delayed internal clock signal at the clock stagger circuit based on the internal clock signal; and capturing a command from an external clock domain into an internal clock domain based on one or both of the internal clock signal and the delayed internal clock signal. - View Dependent Claims (12, 13, 14)
-
-
15. An apparatus, comprising:
-
a memory controller configured to provide a memory read command; and a memory configured to; capture the command from an external clock domain into an internal clock domain synchronously with a delayed internal clock signal; speed up propagation of the command through a shift circuit such that the command is synchronous with an internal clock; and provide data responsive to the read command including providing data at an expected time based on a specified latency. - View Dependent Claims (16, 17, 18, 19, 20)
-
Specification