Systems and methods for reducing standby power in floating body memory devices
First Claim
1. A method of reducing standby power for a floating body memory array having a plurality of floating body memory cells configured with DNWell nodes that can be powered to maintain a high potential in the floating body by a vertical bipolar holding mechanism, said method comprising:
- performing at least one of;
periodically pulsing a source line of the array;
periodically pulsing a bit line of the array;
periodically floating the source line;
or periodically floating the bit line;
wherein said periodically pulsing comprises cyclically applying a pulse of positive voltage to said source line or bit line to turn off the vertical bipolar holding mechanism; and
removing said positive voltage between said pulses to turn on said vertical bipolar holding mechanism.
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Abstract
Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.
239 Citations
3 Claims
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1. A method of reducing standby power for a floating body memory array having a plurality of floating body memory cells configured with DNWell nodes that can be powered to maintain a high potential in the floating body by a vertical bipolar holding mechanism, said method comprising:
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performing at least one of;
periodically pulsing a source line of the array;
periodically pulsing a bit line of the array;
periodically floating the source line;
or periodically floating the bit line;wherein said periodically pulsing comprises cyclically applying a pulse of positive voltage to said source line or bit line to turn off the vertical bipolar holding mechanism; and
removing said positive voltage between said pulses to turn on said vertical bipolar holding mechanism. - View Dependent Claims (2, 3)
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Specification