Digital signaling processing for three dimensional flash memory arrays

• US 9,536,612 B1
• Filed: 01/23/2014
• Issued: 01/03/2017
• Est. Priority Date: 01/23/2014
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Weingarten, Hanan, Sabbag, Erez
• Primary Examiner(s): Nguyen, Vanthu
• Application Number:
  US14/162,493
• Time in Patent Office: 1,076 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/562 Multilevel memory programming aspects
• CPC Class Codes: G11C 2211/5622 Concurrent multilevel programming of more than one cell
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor

Abstract

A method for multilevel programming flash memory cells of a three dimensional array of flash memory cells, the method may include receiving or determining a multiple phase programming scheme that is responsive to coupling between flash memory cells of the three dimensional array; and programming data to multiple flash memory cells of the three dimensional array in response to the multiple phase programming scheme. The multiple phase programming scheme determine a manner in which multiple programming levels are applied. At least two programming levels of the multiple programming levels correspond to bits of different significance.

Claims

1. A method for multilevel programming flash memory cells of a three dimensional array of flash memory cells, the method comprising:

receiving or determining a multiple phase programming scheme that is responsive to coupling between flash memory cells of the three dimensional array; and

programming data to multiple flash memory cells of the three dimensional array in response to the multiple phase programming scheme;

wherein the multiple phase programming scheme determine a manner in which multiple programming levels are applied;

wherein at least two programming levels of the multiple programming levels correspond to bits of different significance;

wherein the three dimensional array comprises multiple planes of flash memory cells, each plane comprise multiple rows and columns of flash memory cells; and

wherein the multiple phase programming scheme determines an order of programming pages, wherein the order of programming pages is responsive to coupling between flash memory cells that belong to different planes.

2. The method according to claim 1 wherein flash memory cells of a same page are programmed concurrently.

3. The method according to claim 2 wherein the multiple phase programming scheme determines to apply a certain level of programming of all pages before starting programming another level of programming of any of the pages, the other level is higher than the certain level.

4. The method according to claim 3 wherein the pages are arranged in an ordered array and wherein the multiple phase programming scheme determines to apply the certain level of programming on one group of pages after the other.

5. The method according to claim 4 wherein each group of pages comprises pages located along a same virtual line.

6. The method according to claim 5 wherein each virtual line orthogonal to a plane.

7. The method according to claim 5 wherein each virtual line is neither parallel or orthogonal to a plane.

8. The method according to claim 1 wherein the multiple phase programming scheme comprises virtually partitioning the three dimensional array to multiple three dimensional subarrays.

9. The method according to claim 8 wherein each three dimensional subarray comprises multiple erase blocks.

10. The method according to claim 8 wherein the multiple phase programming scheme defines at least one programming rule that is responsive to a distance between a flash memory cell that belong to a certain three dimensional subarray and to an adjacent three dimensional subarray.

22. The method according to claim 1, wherein one of the following is true:

(i) the multiple phase programming scheme determines, (a) for a first programming level, a diagonal programming order of pages of each plane of the three dimensional array, and (b) for a second programming level, a column based programming; and

(ii) the multiple phase programming scheme determines a diagonal programming order of pages of each plane of the three dimensional array.

11. A method for multilevel programming flash memory cells of a three dimensional array of flash memory cells, the method comprising:

receiving or determining a multiple phase programming scheme that is responsive to coupling between flash memory cells of the three dimensional array; and

programming data to multiple flash memory cells of the three dimensional array in response to the multiple phase programming scheme;

wherein the multiple phase programming scheme determine a manner in which multiple programming levels are applied;

wherein at least two programming levels of the multiple programming levels correspond to bits of different significance;

wherein the multiple phase programming scheme defines (a) an edge programming rule that is associated with edge flash memory cells and (b) a non-edge programming rule that differs from the edge programming rule and is associated with non-edge flash memory cells.

12. The method according to claim 11, wherein the non-edge programming rule defines a denser programming in relation to programming applied by the edge programming rule.

13. The method according to claim 11, wherein the edge programming rule defines programming only a part of the edge flash memory cells while leaving some edge flash memory un-programmed.

14. The method according to claim 11, wherein (a) a first set of first edge memory cells of a first three dimensional subarray and (b) first set of second edge memory cells of a second three dimensional subarray are positioned on both sides of a border between the first and second three dimensional subarrays;

and wherein the edge programming rule defines a programming of the first sets of first and second flash memory cells.

15. The method according to claim 14 wherein the edge programming rule prevents programming of a first subset of first edge memory cells while facilitating programming of a corresponding first subset of second edge memory cell.

16. The method according to claim 15 wherein the edge programming rule facilitates programming of a second subset of first edge memory cells while preventing programming of a corresponding second subset of second edge memory cell.

17. The method according to claim 14 wherein the edge programming rule defines (a) a first edge maximal level for programming a first subset of first edge memory cells, and (b) a second edge maximal level for programming a first subset of second edge memory cells, and wherein the first edge maximal level differs from the second edge maximal level.

18. The method according to claim 11, wherein the edge programming rule defines a programming of the first sets of the flash memory cells in a manner that is opposite to a programming of the second set of flash memory cells.

19. A non-transitory computer readable medium that stores instructions that once executed by the computer cause the computer to execute the stages of:

receiving or determining a multiple phase programming scheme that is responsive to coupling between flash memory cells of a three dimensional array; and

programming data to multiple flash memory cells of the three dimensional array in response to the multiple phase programming scheme;

wherein the multiple phase programming scheme determine a manner in which multiple programming levels are applied;

wherein at least two programming levels of the multiple programming levels correspond to bits of different significance; and

wherein at least one of the following is true;

(i) the three dimensional array comprises multiple planes of flash memory cells, each plane comprise multiple rows and columns of flash memory cells; and

the multiple phase programming scheme determines an order of programming pages, wherein the order of programming pages is responsive to coupling between flash memory cells that belong to different planes;

(ii) the multiple phase programming scheme defines (a) an edge programming rule that is associated with edge flash memory cells and (b) a non-edge programming rule that differs from the edge programming rule and is associated with non-edge flash memory cells;

(iii) the three dimensional array comprises multiple planes of flash memory cells that comprise multiple pages, wherein the multiple pages are programmed one group of pages after the other;

wherein each group of pages comprises pages located along a same virtual line;

wherein each virtual line is orthogonal to a plane;

(iv) the three dimensional array comprises multiple planes of flash memory cells that comprise multiple pages, wherein the multiple pages are programmed one group of pages after the other;

wherein each group of pages comprises pages located along a same virtual line;

wherein each virtual line is neither parallel or orthogonal to a plane; and

(v) the multiple phase programming scheme determines, (a) for a first programming level, a diagonal programming order of pages of each plane of the three dimensional array, and (b) for a second programming level, a column based programming.

23. The non-transitory computer readable medium according to claim 19 wherein the multiple phase programming scheme defines (a) the edge programming rule that is associated with edge flash memory cells and (b) the non-edge programming rule that differs from the edge programming rule and is associated with non-edge flash memory cells.

24. The non-transitory computer readable medium according to claim 19 wherein the three dimensional array comprises multiple planes of flash memory cells, each plane comprises multiple rows and columns of flash memory cells;

and wherein the multiple phase programming scheme determines the order of programming pages, wherein the order of programming pages is responsive to coupling between flash memory cells that belong to different planes.

25. The non-transitory computer readable medium according to claim 19 wherein the three dimensional array comprises multiple planes of flash memory cells that comprise multiple pages, wherein the multiple pages are programmed one group of pages after the other;

wherein each group of pages comprises pages located along the same virtual line;

wherein each virtual line is orthogonal to the plane.

26. The non-transitory computer readable medium according to claim 19 wherein the three dimensional array comprises multiple planes of flash memory cells that comprise multiple pages, wherein the multiple pages are programmed one group of pages after the other;

wherein each group of pages comprises pages located along the same virtual line;

wherein each virtual line is neither parallel or orthogonal to the plane.

27. The non-transitory computer readable medium according to claim 19 wherein the multiple phase programming scheme determines, (a) for the first programming level, the diagonal programming order of pages of each plane of the three dimensional array, and (b) for the second programming level, the column based programming.

20. A memory controller, comprising a memory module for storing a multiple phase programming scheme that is responsive to coupling between flash memory cells of the three dimensional array;

and a write circuit for programming data to multiple flash memory cells of the three dimensional array in response to the multiple phase programming scheme;

wherein the multiple phase programming scheme determine a manner in which multiple programming levels are applied;

wherein at least two programming levels of the multiple programming levels correspond to bits of different significance;

wherein at least one of the following is true;

(i) the three dimensional array comprises multiple planes of flash memory cells, each plane comprise multiple rows and columns of flash memory cells; and

the multiple phase programming scheme determines an order of programming pages, wherein the order of programming pages is responsive to coupling between flash memory cells that belong to different planes;

(ii) the multiple phase programming scheme defines (a) an edge programming rule that is associated with edge flash memory cells and (b) a non-edge programming rule that differs from the edge programming rule and is associated with non-edge flash memory cells;

(iii) the three dimensional array comprises multiple planes of flash memory cells that comprise multiple pages, wherein the multiple pages are programmed one group of pages after the other;

wherein each group of pages comprises pages located along a same virtual line;

wherein each virtual line is orthogonal to a plane;

(iv) the three dimensional array comprises multiple planes of flash memory cells that comprise multiple pages, wherein the multiple pages are programmed one group of pages after the other;

wherein each group of pages comprises pages located along a same virtual line;

wherein each virtual line is neither parallel or orthogonal to a plane; and

(v) the multiple phase programming scheme determines, (a) for a first programming level, a diagonal programming order of pages of each plane of the three dimensional array, and (b) for a second programming level, a column based programming.

28. The memory controller according to claim 20 wherein the multiple phase programming scheme defines (a) the edge programming rule that is associated with edge flash memory cells and (b) the non-edge programming rule that differs from the edge programming rule and is associated with non-edge flash memory cells.

29. The memory controller according to claim 20 wherein the three dimensional array comprises multiple planes of flash memory cells, each plane comprises multiple rows and columns of flash memory cells;

and wherein the multiple phase programming scheme determines the order of programming pages, wherein the order of programming pages is responsive to coupling between flash memory cells that belong to different planes.

30. The memory controller according to claim 20 wherein the three dimensional array comprises multiple planes of flash memory cells that comprise multiple pages, wherein the multiple pages are programmed one group of pages after the other;

wherein each group of pages comprises pages located along the same virtual line;

wherein each virtual line is orthogonal to the plane.

31. The memory controller according to claim 20 wherein the three dimensional array comprises multiple planes of flash memory cells that comprise multiple pages, wherein the multiple pages are programmed one group of pages after the other;

wherein each group of pages comprises pages located along the same virtual line;

wherein each virtual line is neither parallel or orthogonal to the plane.

32. The memory controller according to claim 20 wherein the multiple phase programming scheme determines, (a) for the first programming level, the diagonal programming order of pages of each plane of the three dimensional array, and (b) for a second programming level, the column based programming.

21. A method for multilevel programming flash memory cells of a three dimensional array of flash memory cells, the method comprising:

receiving or determining a multiple phase programming scheme that is responsive to coupling between flash memory cells of the three dimensional array; and

programming data to multiple flash memory cells of the three dimensional array in response to the multiple phase programming scheme;

wherein the multiple phase programming scheme determine a manner in which multiple programming levels are applied;

wherein at least two programming levels of the multiple programming levels correspond to bits of different significance;

wherein the three dimensional array comprises multiple planes of flash memory cells, each plane comprise multiple rows and columns of flash memory cells; and

wherein one of the following is true;

(i) the multiple phase programming scheme determines a diagonal programming order of pages of each plane of the three dimensional array; and

(ii) the multiple phase programming scheme determines, (a) for a first programming level, a diagonal programming order of pages of each plane of the three dimensional array, and (b) for a second programming level, a column based programming.