Laminating system

• US 9,536,755 B2
• Filed: 03/18/2014
• Issued: 01/03/2017
• Est. Priority Date: 06/02/2004
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Watanabe, Ryosuke, Takahashi, Hidekazu, Tsurume, Takuya
• Primary Examiner(s): Hossain, Moazzam
• Application Number:
  US14/217,519
• Publication Number:
  US 20140220745A1
• Time in Patent Office: 1,022 Days
• Field of Search: 438/127
• US Class Current: 1/1
• CPC Class Codes: B32B 2305/342 Chips
• CPC Class Codes: B32B 37/20 involving the assembly of continuous webs only
• CPC Class Codes: B42D 25/45 Associating two or more layers
• CPC Class Codes: G06K 19/07718 the record carrier being manufactured in a continuous process, e.g. using endless rolls
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/0775 arrangements for connecting the integrated circuit to the antenna
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/67126 Apparatus for sealing, encapsulating, glassing, decapsulating or the like processes H01L23/02, H01L23/28
• CPC Class Codes: H01L 21/67132 Apparatus for placing on an insulating substrate, e.g. tape
• CPC Class Codes: H01L 21/67144 Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68354 used to support diced chips prior to mounting
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 156/1089 of discrete laminae to single face of additional lamina
• CPC Class Codes: Y10T 156/1093 with covering of discrete laminae with additional lamina
• CPC Class Codes: Y10T 156/1712 : Indefinite or running length work

Abstract

It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it easier to handle the thin film integrated circuit. The invention provides a laminating system in which rollers are used for supplying a substrate for sealing, receiving IC chips, separating, and sealing. The separation, sealing, and reception of a plurality of thin film integrated circuits can be carried out continuously by rotating the rollers; thus, the production efficiency can be extremely improved. Further, the thin film integrated circuits can be easily sealed since a pair of rollers opposite to each other is used.

Claims

1. A method comprising:

forming a release layer over a first substrate;

forming a circuit over the release layer, the circuit comprising a transistor;

rotating a peeling roller to attach a first surface of the circuit to a second substrate so that the circuit comprising the transistor is separated from the release layer;

rotating a first roller and a second roller to attach a second surface of the circuit to a third substrate;

sealing the circuit between the second substrate and the third substrate by performing a pressure treatment and a heat treatment while the circuit passes between the first roller and the second roller; and

rotating a receiving roller to wind the circuit which is sealed with the second substrate and the third substrate,

wherein the first surface and the second surface are opposed to each other.

2. The method according to claim 1,

wherein the release layer comprises at least one of tungsten, molybdenum, titan, tantalum, niobium, nickel, cobalt, zirconium, zinc, ruthenium, rhodium, palladium, osmium, iridium, and silicon.

3. The method according to claim 1 is a method for forming an IC chip.

4. A method comprising:

forming a release layer over a first substrate;

forming a circuit over the release layer, the circuit comprising a transistor;

attaching a first surface of the circuit to a second substrate so that the circuit comprising the transistor is separated from the release layer;

attaching a second surface of the circuit to a third substrate; and

rotating a first roller and a second roller to seal the circuit,

wherein the first surface and the second surface are opposed to each other, and

wherein the circuit is sealed by performing a pressure treatment and a heat treatment while the circuit passes between the first roller and the second roller.

5. The method according to claim 4 is a method for forming an IC chip.

9. The method according to claim 4,

wherein the release layer comprises at least one of tungsten, molybdenum, titan, tantalum, niobium, nickel, cobalt, zirconium, zinc, ruthenium, rhodium, palladium, osmium, iridium, and silicon.

6. A method comprising:

forming a release layer over a first substrate;

forming a circuit over the release layer, the circuit comprising a transistor;

rotating a peeling roller to attach a first surface of the circuit to a second substrate so that the circuit comprising the transistor is separated from the release layer;

attaching a second surface of the circuit to a third substrate; and

sealing the circuit between the second substrate and the third substrate by performing a pressure treatment and a heat treatment,

wherein the first surface and the second surface are opposed to each other.

7. The method according to claim 6,

wherein the release layer comprises at least one of tungsten, molybdenum, titan, tantalum, niobium, nickel, cobalt, zirconium, zinc, ruthenium, rhodium, palladium, osmium, iridium, and silicon.

8. The method according to claim 6 is a method for forming an IC chip.