Fin-double-gated junction field effect transistor

• US 9,536,789 B1
• Filed: 01/27/2016
• Issued: 01/03/2017
• Est. Priority Date: 01/27/2016
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Ning, Tak H.
• Primary Examiner(s): Vu, David
• Application Number:
  US15/007,616
• Time in Patent Office: 342 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/8232 Field-effect technology
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1058 with PN junction gate
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66893 with a PN junction gate, i.e. JFET
• CPC Class Codes: H01L 29/66901 with a PN homojunction gate
• CPC Class Codes: H01L 29/66916 with a PN heterojunction gate
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence

Abstract

A method of forming a double-gated junction field effect transistors (JFET) and a tri-gated metal-oxide-semiconductor field effect transistor (MOSFET) on a common substrate is provided. The double-gated JFET is formed in a first region of a substrate by forming a semiconductor gate electrode contacting sidewall surfaces of a first channel region of a first semiconductor fin and a top surface of a portion of a first fin cap atop the first channel region. The tri-gated MOSFET is formed in a second region of the substrate by forming a metal gate stack contacting a top surface and sidewall surfaces of a second channel region of a second semiconductor fin.

Claims

1. A method of forming a semiconductor structure comprising:

forming a first sacrificial gate structure straddling a first fin stack of a first semiconductor fin and a first fin cap atop the first semiconductor fin that is located in a first region of a substrate and a second sacrificial gate structure straddling a second fin stack of a second semiconductor fin and a second fin cap atop the second semiconductor fin that is located in a second region of a substrate, wherein the first sacrificial gate structure comprises a first sacrificial gate stack and a first gate spacer located on sidewalls of the first sacrificial gate stack, and the second sacrificial gate structure comprises a second sacrificial gate stack and a second gate spacer located on sidewalls of the second sacrificial gate stack; and

forming, in any order, a junction field effect transistor (JFET) in the first region of the substrate and a metal-oxide-semiconductor field effect transistor (MOSFET) in the second region of the substrate,

wherein the forming the JFET comprises;

removing the first sacrificial gate stack to provide a first gate cavity while covering the second region of the substrate with a patterned first mask layer, the first gate cavity exposing a portion of the first fin cap and a portion of first semiconductor fin,

doping the exposed portion of the first semiconductor fin with dopants of a first conductivity type, and

forming a semiconductor gate electrode over the exposed portion of the first fin cap and the doped exposed portion of the first semiconductor fin, wherein the semiconductor gate electrode comprises dopants of a second conductivity type opposite the first conductivity type; and

wherein the forming the MOSFET comprises;

removing the second sacrificial gate stack to provide a second gate cavity while covering the first region of the substrate with a patterned second mask layer, the second gate cavity exposing a portion of the second fin cap and a portion of the second semiconductor fin,

removing the exposed portion of the second fin cap from top of the second semiconductor fin,

forming a gate dielectric over the exposed portion of the second semiconductor fin, and

forming a metal gate electrode over the gate dielectric.

2. The method of claim 1, wherein each of the first semiconductor fin and the second semiconductor fin comprises a first semiconductor material.

3. The method of claim 2, wherein the semiconductor gate electrode is formed by epitaxially growing a second semiconductor material from sidewalls of the exposed portion of the first semiconductor fin.

4. The method of claim 3, wherein the first semiconductor material is Si and the second semiconductor material is SiGe.

5. The method of claim 2, further comprising doping another portions of the first semiconductor fin that are not covered by the first sacrificial gate stack with the dopants of the first conductivity type to form first fin source/drain regions within the first semiconductor fin and doping another portions of the second semiconductor fin that are not covered by the second sacrificial gate stack with the dopants of the first conductivity type to form second fin source/drain regions within the second semiconductor fin.

6. The method of claim 5, further comprising forming first epitaxial source/drain regions over the another portions of the first semiconductor fin and forming second epitaxial source/drain regions over the another portions of the second semiconductor fin.

7. The method of claim 6, wherein the first epitaxial source/drain regions and the second epitaxial source/drain regions are formed by epitaxially depositing a third semiconductor material different from the first semiconductor material.

8. The method of claim 7, further comprising forming an interlevel dielectric (ILD) layer over the first epitaxial source/drain regions, the second epitaxial source/drain region, the first sacrificial gate structure, the second sacrificial gate structure and the substrate.

9. The method of claim 1, wherein the substrate comprises a buried insulator layer overlying a handle substrate.

10. The method of claim 1, wherein the forming the JFET further comprises forming a first gate cap over the semiconductor gate electrode, and the forming the MOSFET further comprises forming a second gate cap over the gate dielectric and the metal gate electrode.