Semiconductor device allowing metal layer routing formed directly under metal pad

• US 9,536,833 B2
• Filed: 05/26/2016
• Issued: 01/03/2017
• Est. Priority Date: 02/01/2013
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Chen, Chun-Liang
• Primary Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US15/164,889
• Publication Number:
  US 20160268202A1
• Time in Patent Office: 222 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/05085 with additional elements, e.g. vias arrays, interposed between the stacked layers
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5221 Crossover interconnections
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A semiconductor device may include a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device and is directly contacting the first metal layer. The first specific metal layer routing is formed on a second metal layer of the semiconductor device and under the metal pad. In addition, the semiconductor device may include at least one via plug for connecting the first specific metal layer routing to at least one metal region in the first metal layer, where the aforementioned at least one via plug is formed directly under the metal pad.

Claims

1. A semiconductor device, comprising:

a metal pad, positioned on a first metal layer of the semiconductor device and directly contacting the first metal layer;

a first specific metal layer routing, formed on a second metal layer of the semiconductor device and under the metal pad; and

at least one via plug for connecting the first specific metal layer routing to at least one metal region in the first metal layer, wherein the via plug is formed directly under the metal pad.

2. The semiconductor device of claim 1, wherein the metal pad has a thickness smaller than 20 KA.

3. The semiconductor device of claim 1, wherein material of the metal pad is aluminum.

4. The semiconductor device of claim 1, wherein the first specific metal layer routing has a uniform pattern.

5. The semiconductor device of claim 4, wherein the uniform pattern has a metal density range between 30% and 70%.

6. The semiconductor device of claim 1, wherein the first specific metal layer routing comprises a plurality of sets of terminal lines corresponding to terminals of a plurality of field effect transistors (FETs), respectively.

7. The semiconductor device of claim 6, wherein there are oxide regions between the plurality of sets of terminal lines, and each oxide region has a width greater than 2 micrometers.

8. The semiconductor device of claim 6, wherein a set of terminal lines within the plurality of sets of terminal lines comprises a source terminal line and a drain terminal line respectively corresponding to a source terminal and a drain terminal of a FET within the plurality of FETs.

9. The semiconductor device of claim 8, wherein there is an oxide region between the source terminal line and the drain terminal line, and the oxide region has a width greater than 2 micrometers.

10. The semiconductor device of claim 1, further comprising:

a second specific metal layer routing, formed on the second metal layer of the semiconductor device and connected to the first specific metal layer routing, wherein the second specific metal layer routing is not directly positioned under the metal pad.

11. The semiconductor device of claim 10, wherein the first specific metal layer routing comprises a plurality of sets of terminal lines corresponding to terminals of a plurality of field effect transistors (FETs), respectively;

and the second specific metal layer routing comprises a plurality of sets of terminal lines corresponding to the plurality of sets of terminal lines of the first specific metal layer routing, respectively.

12. The semiconductor device of claim 11, wherein the plurality of sets of terminal lines of the second specific metal layer routing are extensions of the plurality of sets of terminal lines of the first specific metal layer routing, respectively.

13. The semiconductor device of claim 1, wherein the semiconductor device is a chip.

14. The semiconductor device of claim 1, wherein the first metal layer and the second metal layer are adjacent metal layers of the semiconductor device.

15. The semiconductor device of claim 1, wherein at least one size of at least one side of the at least one via plug is not less than 1 micrometer.

16. The semiconductor device of claim 15, wherein a size of a first side of the at least one via plug is not less than 1 micrometer, and a size of a second side of the at least one via plug is not less than 3 micrometers.

17. The semiconductor device of claim 1, wherein the at least one via plug comprises multiple via plugs, directly under the metal pad.