Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods

• US 9,536,840 B2
• Filed: 02/12/2013
• Issued: 01/03/2017
• Est. Priority Date: 02/12/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Du, Yang
• Primary Examiner(s): Jung, Michael
• Assistant Examiner(s): Chang, Jay C
• Application Number:
  US13/765,061
• Publication Number:
  US 20140225235A1
• Time in Patent Office: 1,421 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 23/373 Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A three-dimensional (3-D) integrated circuit (3DIC) with a graphene shield is disclosed. In certain embodiments, at least a graphene layer is positioned between two adjacent tiers of the 3DIC. A graphene layer is a sheet like layer made of pure carbon, at least one atom thick with atoms arranged in a regular hexagonal pattern. A graphene layer may be disposed between any number of adjacent tiers in the 3DIC. In exemplary embodiments, the graphene layer provides an electromagnetic interference shield between adjacent tiers or layers in the 3DIC to reduce crosstalk between the tiers. In other exemplary embodiments, the graphene layer(s) can be disposed in the 3DIC to provide a heat sink that directs and dissipates heat to peripheral areas of the 3DIC. In some embodiments, the graphene layer(s) are configured to provide both EMI shielding and heat shielding.

Claims

1. A monolithic three-dimensional (3-D) integrated circuit (3DIC), comprising:

a first semiconductor integrated circuit tier comprising a first one or more active components;

a second semiconductor integrated circuit tier comprising a second one or more active components vertically positioned relative to the first semiconductor integrated circuit tier; and

at least one graphene layer disposed between the first and second semiconductor integrated circuit tiers and extending from a first exterior edge of the monolithic 3DIC to a second opposite exterior edge of the monolithic 3DIC, the at least one graphene layer electrically isolated from all active components in the first and second semiconductor integrated circuit tiers, wherein the at least one graphene layer is coupled to ground.

2. The monolithic 3DIC of claim 1, wherein the at least one graphene layer provides electromagnetic shielding between the first and second semiconductor integrated circuit tiers.

3. The monolithic 3DIC of claim 1, wherein the at least one graphene layer is configured to conduct heat away from interiorly positioned active elements within the first and second semiconductor integrated circuit tiers.

4. The monolithic 3DIC of claim 1, wherein the at least one graphene layer defines at least one aperture.

5. The monolithic 3DIC of claim 4, further comprising a conductive via passing through the at least one aperture and coupling a first active component of the first one or more active components in the first semiconductor integrated circuit tier and a second active component of the second one or more active components in the second semiconductor integrated circuit tier.

6. The monolithic 3DIC of claim 1, further comprising a thermal via thermally contiguous to the at least one graphene layer.

7. The monolithic 3DIC of claim 4, wherein the at least one aperture is proximate the first exterior edge.

8. The monolithic 3DIC of claim 4, wherein the monolithic 3DIC comprises a center and the at least one aperture is proximate the center.

9. The monolithic 3DIC of claim 4, wherein the at least one aperture is spaced inwardly from the first exterior edge.

10. The monolithic 3DIC of claim 7, further comprising a thermal via positioned proximate the first exterior edge.

11. The monolithic 3DIC of claim 1, further comprising a bonding layer bonding the first semiconductor integrated circuit tier to the second semiconductor integrated circuit tier and wherein the at least one graphene layer is positioned below the bonding layer.

12. The monolithic 3DIC of claim 11, wherein the bonding layer comprises an annealed oxide layer.

13. The monolithic 3DIC of claim 1 integrated into a semiconductor die.

14. The monolithic 3DIC of claim 1, further comprising a device selected from the group consisting of:

a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player, into which the monolithic 3DIC is integrated.

15. A monolithic three-dimensional (3-D) integrated circuit (3DIC), comprising:

a first means for providing a semiconductor tier comprising a first one or more active components;

a second means for providing a semiconductor tier comprising a second one or more active components vertically positioned relative to the first means for providing the semiconductor tier; and

at least one graphene layer disposed between the first and second means for providing the semiconductor tiers and extending from a first exterior edge of the monolithic 3DIC to a second opposite exterior edge of the monolithic 3DIC, the at least one graphene layer electrically isolated from all active components in the semiconductor tiers, wherein the at least one graphene layer is coupled to ground.