Display device
First Claim
Patent Images
1. A liquid crystal display device comprising:
- a gate driver circuit formed over a substrate, the gate driver circuit comprising;
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor; and
a seventh transistor; and
a pixel formed over the substrate, the pixel comprising;
an eighth transistor;
a first conductive layer; and
a second conductive layer,wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,wherein one of a source and a drain of the third transistor is electrically connected to a fourth wiring,wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the second transistor,wherein a gate of the third transistor is electrically connected to a fifth wiring,wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the second transistor,wherein a gate of the fourth transistor is electrically connected to a sixth wiring,whrerein one of a source and a drain of the fifth transistor is electrically connected to a seventh wiring,wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor,wherein a gate of the fifth transistor is electrically connected to an eighth wiring,wherein one of a source and a drain of the sixth transistor is electrically connected to the third wiring,wherein the other of the source and the drain of the sixth transistor is electrically connected to the other of the source and the drain of the fifth transistor,wherein a gate of the sixth transistor is electrically connected to the gate of the second transistor,wherein one of a source and a drain of the seventh transistor is electrically connected to the third wiring,wherein the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor,wherein a gate of the seventh transistor is electrically connected to the other of the source and the drain of the fifth transistor,wherein a ratio of a channel width to a channel length of the first transistor is larger than a ratio of a channel width to a channel length of the third transistor,wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fourth transistor,wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fifth transistor,wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the sixth transistor,wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the seventh transistor,wherein a first insulating film is over the eighth transistor,wherein the first conductive layer is over the first insulating film,wherein a second insulating film is over the first conductive layer,wherein the second conductive layer is over the second insulating film,wherein a liquid crystal is over the second conductive layer,wherein the second insulating film comprises a part which is sandwiched by the first conductive layer and the second conductive layer,wherein a gate of the eighth transistor is electrically connected to the second wiring,wherein the first insulating film comprises a first contact hole,wherein the second insulating film comprises a second contact hole, andwherein the second conductive layer is electrically connected to one of a source and a drain of the eighth transistor through the second contact hole and the first contact hole.
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Accused Products
Abstract
To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.
141 Citations
8 Claims
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1. A liquid crystal display device comprising:
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a gate driver circuit formed over a substrate, the gate driver circuit comprising; a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; and a seventh transistor; and a pixel formed over the substrate, the pixel comprising; an eighth transistor; a first conductive layer; and a second conductive layer, wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring, wherein one of a source and a drain of the second transistor is electrically connected to a third wiring, wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring, wherein one of a source and a drain of the third transistor is electrically connected to a fourth wiring, wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the second transistor, wherein a gate of the third transistor is electrically connected to a fifth wiring, wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring, wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the second transistor, wherein a gate of the fourth transistor is electrically connected to a sixth wiring, whrerein one of a source and a drain of the fifth transistor is electrically connected to a seventh wiring, wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor, wherein a gate of the fifth transistor is electrically connected to an eighth wiring, wherein one of a source and a drain of the sixth transistor is electrically connected to the third wiring, wherein the other of the source and the drain of the sixth transistor is electrically connected to the other of the source and the drain of the fifth transistor, wherein a gate of the sixth transistor is electrically connected to the gate of the second transistor, wherein one of a source and a drain of the seventh transistor is electrically connected to the third wiring, wherein the other of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor, wherein a gate of the seventh transistor is electrically connected to the other of the source and the drain of the fifth transistor, wherein a ratio of a channel width to a channel length of the first transistor is larger than a ratio of a channel width to a channel length of the third transistor, wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fourth transistor, wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fifth transistor, wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the sixth transistor, wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the seventh transistor, wherein a first insulating film is over the eighth transistor, wherein the first conductive layer is over the first insulating film, wherein a second insulating film is over the first conductive layer, wherein the second conductive layer is over the second insulating film, wherein a liquid crystal is over the second conductive layer, wherein the second insulating film comprises a part which is sandwiched by the first conductive layer and the second conductive layer, wherein a gate of the eighth transistor is electrically connected to the second wiring, wherein the first insulating film comprises a first contact hole, wherein the second insulating film comprises a second contact hole, and wherein the second conductive layer is electrically connected to one of a source and a drain of the eighth transistor through the second contact hole and the first contact hole. - View Dependent Claims (2, 3, 4)
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5. A liquid crystal display device comprising:
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a gate driver circuit formed over a substrate, the gate driver circuit comprising; a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; and a seventh transistor; and a pixel formed over the substrate, the pixel comprising; an eighth transistor; a first conductive layer; and a second conductive layer, wherein one of a source and a drain of the first transistor is directly connected to a first wiring, wherein the other of the source and the drain of the first transistor is directly connected to a second wiring, wherein one of a source and a drain of the second transistor is directly connected to a third wiring, wherein the other of the source and the drain of the second transistor is directly connected to the second wiring, wherein one of a source and a drain of the third transistor is directly connected to a fourth wiring, wherein the other of the source and the drain of the third transistor is directly connected to a gate of the second transistor, wherein a gate of the third transistor is electrically connected to a fifth wiring, wherein one of a source and a drain of the fourth transistor is directly connected to the third wiring, wherein the other of the source and the drain of the fourth transistor is directly connected to the gate of the second transistor, wherein a gate of the fourth transistor is directly connected to a sixth wiring, whrerein one of a source and a drain of the fifth transistor is directly connected to a seventh wiring, wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor, wherein a gate of the fifth transistor is directly connected to an eighth wiring, wherein one of a source and a drain of the sixth transistor is directly connected to the third wiring, wherein the other of the source and the drain of the sixth transistor is directly connected to the other of the source and the drain of the fifth transistor, wherein a gate of the sixth transistor is directly connected to the gate of the second transistor, wherein one of a source and a drain of the seventh transistor is directly connected to the third wiring, wherein the other of the source and the drain of the seventh transistor is directly connected to the gate of the second transistor, wherein a gate of the seventh transistor is directly connected to the other of the source and the drain of the fifth transistor, wherein a ratio of a channel width to a channel length of the first transistor is larger than a ratio of a channel width to a channel length of the third transistor, wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fourth transistor, wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the fifth transistor, wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the sixth transistor, wherein the ratio of the channel width to the channel length of the first transistor is larger than a ratio of a channel width to a channel length of the seventh transistor, wherein a first insulating film is over the eighth transistor, wherein the first conductive layer is over the first insulating film, wherein a second insulating film is over the first conductive layer, wherein the second conductive layer is over the second insulating film, wherein a liquid crystal is over the second conductive layer, wherein the second insulating film comprises a part which is sandwiched by the first conductive layer and the second conductive layer, wherein a gate of the eighth transistor is directly connected to the second wiring, wherein the first insulating film comprises a first contact hole, wherein the second insulating film comprises a second contact hole, wherein the eighth transistor comprises a semiconductor layer comprising polycrystalline silicon, wherein a third conductive layer is incontact with a side surface of the semiconductor layer, and wherein the second conductive layer is in contact with the third conductive layer through the second contact hole and the first contact hole. - View Dependent Claims (6, 7, 8)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsUmezaki, Atsushi, Miyake, Hiroyuki
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Primary Examiner(s)XAVIER, ANTONIO J
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Application NumberUS14/548,365Publication NumberTime in Patent Office775 DaysField of SearchNoneUS Class Current1/1CPC Class CodesG09G 2300/0809 Several active elements per...G09G 2310/0205 Simultaneous scanning of se...G09G 2310/0248 Precharge or discharge of c...G09G 2310/0286 Details of a shift register...G09G 2310/0289 Details of voltage level sh...G09G 2310/0291 Details of output amplifier...G09G 2310/061 for resetting or blankingG09G 2320/0646 Modulation of illumination ...G09G 2320/0666 for control of colour param...G09G 3/2092 Details of a display termin...G09G 3/3266 Details of drivers for scan...G09G 3/3674 Details of drivers for scan...G09G 3/3677 suitable for active matrice...G11C 19/28 using semiconductor element...H01L 27/0207 Geometrical layout of the c...H01L 27/1222 with a particular compositi...H01L 27/1225 with semiconductor material...H01L 27/124 with a particular compositi...
