Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls

• US 9,536,971 B2
• Filed: 12/05/2014
• Issued: 01/03/2017
• Est. Priority Date: 07/08/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Primary Examiner(s): Tran, Tony
• Application Number:
  US14/561,605
• Publication Number:
  US 20150108566A1
• Time in Patent Office: 760 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a recess in the wafer. A conductive transistor gate layer is then formed within the trench and over the vertical spacing layer. The transistor gate layer is etched, which exposes the vertical spacing layer. A spacer layer is formed over the etched conductive gate layer and over the vertical spacing layer, then the spacer layer and the vertical spacing layer are anisotropically etched. Subsequent to anisotropically etching the vertical spacing layer, a portion of the vertical spacing layer is interposed between the semiconductor wafer and the etched conductive transistor gate layer in a direction perpendicular to the plane of a major surface of the semiconductor wafer.

Claims

1. A semiconductor device comprising:

a transistor comprising a conductive gate within and projecting elevationally outward of a trench in semiconductive material;

a gate dielectric within the trench between the conductive gate and the semiconductive material;

the conductive gate comprising opposing laterally outermost vertically oriented conductive gate sidewalls that are elevationally outward of the semiconductive material laterally outward of semiconductive material sidewalls of the trench, “

elevationally” and

“

laterally”

being with respect to two different directions that are perpendicular relative to one another, the gate comprising opposing laterally inner vertically oriented conductive gate sidewalls elevationally outward of the semiconductive material;

a dielectric spacer along each of the laterally outermost vertical gate sidewalls; and

a dielectric vertical spacing layer elevationally inward of the laterally outermost vertical gate sidewall on each of opposing sides of the gate, the vertical spacing layer extending laterally outward and laterally inward relative to the laterally outermost vertical gate sidewall on each of the opposing sides of the conductive gates, at least one of the dielectric vertical spacing layers on one of the opposing sides of the gate having a first portion that is under the gate and above the semiconductive material on that one opposing gate side and having a second portion that is under the spacer and above the semiconductive material on that one opposing gate side, the first portion that is under the gate being elevationally thicker than the second portion that is under the spacer, the first portion having a laterally outer sidewall on that one opposing gate side, the dielectric spacer on that one opposing gate side being directly against the first portion laterally outer sidewall on that one opposing gate side, no part of the second portion on that one opposing gate side being directly against the conductive gate.

2. The device of claim 1 comprising a pad dielectric elevationally between the dielectric vertical spacing layer and the semiconductive material on each of the opposing sides of the conductive gate.

3. A semiconductor device comprising:

a transistor comprising a conductive gate within and projecting elevationally outward of a trench in semiconductive material;

a gate dielectric within the trench between the conductive gate and the semiconductive material;

the conductive gate comprising opposing laterally outermost vertically oriented conductive gate sidewalls that are elevationally outward of the semiconductive material laterally outward of semiconductive material sidewalls of the trench, “

elevationally” and

“

laterally”

being with respect to two different directions that are perpendicular relative to one another, the gate comprising opposing laterally inner vertically oriented conductive gate sidewalls elevationally outward of the semiconductive material;

a dielectric spacer along each of the laterally outermost vertical gate sidewalls; and

a dielectric vertical spacing layer elevationally inward of the laterally outermost vertical gate sidewall on each of opposing sides of the gate, the vertical spacing layer extending laterally outward and laterally inward relative to the laterally outermost vertical gate sidewall on each of the opposing sides of the conductive gates, the dielectric vertical spacing layers on each of the opposing sides of the gate having a first portion that is under the gate and above the semiconductive material and having a second portion that is under the spacer and above the semiconductive material, the first portion that is under the gate being elevationally thicker than the second portion that is under the spacer on each of the opposing gate sides, the first portion having a laterally outer sidewall on each of the opposing gate sides, the dielectric spacer on each of the opposing gate sides being directly against the first portion laterally outer sidewall on each of the opposing gate sides, no part of the second portion on each of the opposing gate sides being directly against the conductive gate.