Semiconductor device with charge compensation

• US 9,537,003 B2
• Filed: 08/13/2014
• Issued: 01/03/2017
• Est. Priority Date: 03/07/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Weber, Hans, Gamerith, Stefan, Hirler, Franz
• Primary Examiner(s): Page, Dale E
• Assistant Examiner(s): Hillman, Damian A
• Application Number:
  US14/458,616
• Publication Number:
  US 20140346589A1
• Time in Patent Office: 874 Days
• Field of Search: 257/340
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02365 Forming inorganic semiconducting materials on a substrate for light-sensitive devices H01L31/00
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H03K 17/06 Modifications for ensuring a fully conducting state

Abstract

A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first semiconductor layer including a compensation-structure; a second semiconductor layer adjoining the first layer, comprised of semiconductor material of a first conductivity type and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; a third semiconductor layer of the first conductivity type adjoining the second layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third layer; and a fourth semiconductor layer of the first conductivity type adjoining the third layer and having a maximum doping concentration higher than that of the third layer. The first semiconductor layer is arranged between the first surface and the second semiconductor layer.

Claims

1. A semiconductor device, comprising a semiconductor body having a first surface defining a vertical direction, and a source metallization arranged on the first surface, wherein in a vertical cross-section the semiconductor body comprises:

a drift region of a first conductivity type;

at least two field plates each of which is disposed in the drift region, separated from the drift region by a field dielectric layer and in ohmic contact with the source metallization;

a drain region of the first conductivity type having a maximum doping concentration higher than a maximum doping concentration of the drift region; and

a third semiconductor layer of the first conductivity type arranged between the drift region and the drain region and comprising at least one of a floating field plate and a floating semiconductor region of a second conductivity type forming a pn-junction with the third semiconductor layer,

wherein the semiconductor device further comprises a drain metallization in ohmic contact with the drain region,

wherein the drift region is substantially depletable at a reverse voltage applied between the source metallization and the drain metallization that is lower than a rated breakdown voltage of the semiconductor device.

2. The semiconductor device of claim 1, further comprising a second semiconductor layer comprised of a semiconductor material of the first conductivity type, arranged between and adjoining the drift region and the third semiconductor layer and having a doping charge per horizontal area which is lower than a breakdown charge per area of the semiconductor material.

3. The semiconductor device of claim 1, wherein each of the at least two field plates is arranged in a lower portion of a vertical trench extending from the first surface partly into the drift region.

4. The semiconductor device of claim 1, further comprising a body region of the second conductivity type adjoining the drift region and arranged between the first surface and the drift region, and wherein the at least two field plates are arranged below the body region.

5. The semiconductor device of claim 1, wherein the at least two field plates extend, in the vertical direction, substantially along the drift region.

6. The semiconductor device of claim 1, wherein the floating semiconductor region is, in the vertical cross-section, a substantially vertically orientated pillar or a substantially vertically orientated strip-type parallelepiped.

7. The semiconductor device of claim 1, wherein the third semiconductor layer is arranged below the drift region.

8. The semiconductor device of claim 1, wherein the third semiconductor layer comprises at least two spaced apart floating semiconductor regions arranged vertically below each other.

9. A semiconductor device, comprising a semiconductor body comprising:

a first surface defining a vertical direction;

a first semiconductor layer comprising a compensation structure;

a second semiconductor layer adjoining the first semiconductor layer, being comprised of a semiconductor material of a first conductivity type, and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material, the first semiconductor layer being arranged between the first surface and the second semiconductor layer;

a third semiconductor layer of the first conductivity type adjoining the second semiconductor layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third semiconductor layer; and

a fourth semiconductor layer of the first conductivity type adjoining the third semiconductor layer and having a maximum doping concentration which is higher than a maximum doping concentration of the third semiconductor layer.

10. The semiconductor device of claim 9, wherein the first semiconductor layer is of the first conductivity type and comprises, in a vertical cross-section, at least two compensation regions of the second conductivity type, each of the at least two compensation regions forming a pn-junction with a first portion of the first semiconductor layer, the first portion of the first semiconductor layer being arranged between the at least two compensation regions and forming a pn-compensation-structure with the at least two compensation regions.

11. The semiconductor device of claim 9, wherein the first semiconductor layer is of the first conductivity type and comprises, in a vertical cross-section, at least two field plates each of which is separated from a first portion of the first semiconductor layer by a field dielectric layer, the first portion of the first semiconductor layer being arranged between the at least two field plates and forming a field-plate compensation-structure with the at least two field plates and the respective field dielectric layers.

12. The semiconductor device of claim 9, further comprising a source metallization arranged on the first surface in low resistive contact with the at least two compensation regions, and a drain metallization in ohmic contact with the fourth semiconductor layer, wherein the first semiconductor layer is substantially depletable at a reverse voltage between the source metallization and the drain metallization lower than a rated breakdown voltage of the semiconductor device.

13. The semiconductor device of claim 9, wherein the semiconductor region is a floating semiconductor region.

14. The semiconductor device of claim 9, wherein the third semiconductor layer comprises an upper portion adjoining the second semiconductor layer and a lower portion adjoining the fourth semiconductor layer and arranged below the self-charging charge trap, and wherein at least one of the floating field plate and the semiconductor region is of the second conductivity type.

15. A method for producing a semiconductor device, the method comprising:

providing a semiconductor body of a first conductivity type comprising a top surface defining a vertical direction, and a backside surface arranged opposite the top surface;

forming in the semiconductor body from the top surface at least one of a floating trench field plate which is partly separated from the semiconductor body by a dielectric region and a floating semiconductor region of a second conductivity type forming a pn-junction within the semiconductor body;

epitaxial depositing at least two semiconductor layers of the first conductivity type on the top surface;

forming in an upper semiconductor layer of the at least two semiconductor layers a compensation-structure; and

forming a first metallization above the at least two semiconductor layers and in ohmic contact with the compensation-structure.