Semiconductor device structure and method for forming the same

• US 9,537,010 B2
• Filed: 02/04/2015
• Issued: 01/03/2017
• Est. Priority Date: 02/04/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Fang, Ziwei, Wang, Tsan-Chun, Chan, Chien-Tai, Lin, Da-Wen, Chang, Huicheng
• Primary Examiner(s): Nhu, David
• Application Number:
  US14/613,663
• Publication Number:
  US 20160225906A1
• Time in Patent Office: 699 Days
• Field of Search: 438/197, 438/270, 438/104, 438/692, 438/680, 438/700, 257/288, 257/350, 257/396, 257/E21.006, 257/E21.014, 257/E21.023, 257/E21.051, 257/E21.077, 257/E21.126, 257/E21.127, 257/E21.147, 257/E21.17, 257/E21.231, 257/E21.247, 257/E21.248, 257/E21.253, 257/E21.267, 257/E21.304, 257/E21.229, 257/E21.435
• US Class Current: 1/1
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a doped region in an upper portion of the substrate. The doped region is doped with first dopants of a first conduction type. The semiconductor device structure includes one fin structure over the substrate. A first dopant concentration of the doped region exposed by the fin structure is greater than a second dopant concentration of the doped region covered by the fin structure. The semiconductor device structure includes an isolation layer over the substrate and at two opposite sides of the fin structure. The semiconductor device structure includes a gate over the isolation layer and the fin structure.

Claims

1. A semiconductor device structure, comprising:

a substrate having a doped region in an upper portion of the substrate, wherein the doped region is doped with first dopants of a first conduction type;

at least one fin structure over the substrate, wherein a first dopant concentration of the doped region exposed by the fin structure is greater than a second dopant concentration of the doped region covered by the fin structure;

an isolation layer over the substrate and surrounding the fin structure;

a gate over the isolation layer and the fin structure; and

a source structure and a drain structure over the fin structure and at two opposite sides of the gate, wherein the source structure and the drain structure are doped with second dopants of a second conduction type, and the second conduction type is opposite to the first conduction type.

2. The semiconductor device structure as claimed in claim 1, wherein a third dopant concentration of the source structure or the drain structure is greater than the first dopant concentration.

3. The semiconductor device structure as claimed in claim 1, wherein the substrate has a doped well doped with third dopants, the doped well is under the doped region, the first dopants and the third dopants are made of a same material, and the doped well has a third dopant concentration, which is less than the second dopant concentration.

4. The semiconductor device structure as claimed in claim 1, wherein the substrate comprises a lower portion and the upper portion over the lower portion, and a first width of the upper portion is less than a second width of the lower portion.

5. The semiconductor device structure as claimed in claim 1, wherein the doped region is adjacent to a first upper surface and a sidewall of the upper portion.

6. The semiconductor device structure as claimed in claim 5, wherein the isolation layer covers the first upper surface and the sidewall of the upper portion and a second upper surface of the lower portion.

7. A semiconductor device structure, comprising:

a substrate having a doped region in an upper portion of the substrate, wherein the doped region is doped with first dopants of a first conduction type, the substrate comprises a lower portion, the upper portion is over the lower portion, and a first width of the upper portion is less than a second width of the lower portion;

at least one fin structure over the substrate;

a first diffusion layer over the substrate and a first lower portion of a first sidewall of the fin structure, wherein the first diffusion layer comprises second dopants, and the second dopants and the first dopants are made of a same material;

an isolation layer over the first diffusion layer; and

a gate over the isolation layer and the fin structure.

8. The semiconductor device structure as claimed in claim 7, wherein a first dopant concentration of the doped region exposed by the fin structure is greater than a second dopant concentration of the doped region covered by the fin structure.

9. The semiconductor device structure as claimed in claim 7, wherein a first dopant concentration of the first diffusion layer is greater than a second dopant concentration of the doped region.

10. The semiconductor device structure as claimed in claim 7, wherein the first diffusion layer surrounds the fin structure.

11. The semiconductor device structure as claimed in claim 7, further comprising:

a second diffusion layer over the first diffusion layer, wherein the second diffusion layer comprises third dopants of a second conduction type, and the second conduction type is opposite to the first conduction type.

12. The semiconductor device structure as claimed in claim 7, wherein the first diffusion layer conformally covers the first sidewall of the fin structure, a first upper surface and a second sidewall of the upper portion, and a second upper surface of the lower portion.

13. The semiconductor device structure as claimed in claim 7, wherein the first diffusion layer is in direct contact with the substrate and the fin structure.

14. A method for forming a semiconductor device structure, comprising:

providing a substrate, a fin structure, a dielectric layer, and a mask layer, wherein the fin structure is over the substrate, the dielectric layer is over the fin structure, and the mask layer is over the dielectric layer;

performing an implantation process on the substrate exposed by the mask layer to form doped regions in the substrate;

forming an isolation layer over the substrate;

removing the dielectric layer and the mask layer;

performing an annealing process on the substrate to enlarge the doped regions so as to merge the doped regions into a merged doped region; and

form a gate over the fin structure and the isolation layer.

15. The method for forming a semiconductor device structure as claimed in claim 14, further comprising:

after the implantation process and before the annealing process, removing a portion of the substrate to form a trench in the substrate, wherein the trench surrounds the fin structure and the doped regions.

16. The method for forming a semiconductor device structure as claimed in claim 14, wherein the mask layer comprises nitride.

17. The method for forming a semiconductor device structure as claimed in claim 14, wherein the doped regions are doped with first dopants of a first conduction type, and the method further comprises:

after the implantation process and before the formation of the isolation layer, forming a first diffusion layer over the substrate and a lower portion of a sidewall of the fin structure, wherein the first diffusion layer comprises second dopants, the first dopants and the second dopants are made of a same material, and the isolation layer is formed over the first diffusion layer.

18. The method for forming a semiconductor device structure as claimed in claim 17, further comprising:

after the formation of the first diffusion layer and before the formation of the isolation layer, forming a second diffusion layer over the first diffusion layer, wherein the second diffusion layer comprises third dopants of a second conduction type, the second conduction type is opposite to the first conduction type, and the isolation layer is formed over the second diffusion layer.