Partially dielectric isolated fin-shaped field effect transistor (FinFET)

• US 9,537,011 B1
• Filed: 12/14/2015
• Issued: 01/03/2017
• Est. Priority Date: 12/14/2015
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Divakaruni, Ramachandra, Faltermeier, Johnathan E., Nowak, Edward J., Rim, Kern
• Primary Examiner(s): Schoenholtz, Joseph
• Application Number:
  US14/968,816
• Time in Patent Office: 386 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 2029/7857 of the accumulation type
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/31105 Etching inorganic layers
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76202 using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO H01L21/76235 takes precedence; together with vertical isolation, e.g. LOCOS in a SOI substrate, H01L21/76264
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

One embodiment provides a method comprising etching a fin of a fin-shaped field effect transistor (FinFET) to form a reduced fin, and laterally etching the reduced fin to form a fin channel including a first fin channel sidewall and a second fin channel sidewall opposing the first fin channel sidewall. The method further comprises forming a first thin dielectric tunnel and a second thin dielectric tunnel on the first fin channel sidewall and the second fin channel sidewall, respectively. Each thin dielectric tunnel prevents lateral epitaxial crystal growth on the fin channel. The method further comprises etching an insulator layer disposed between the fin channel and a substrate of the FinFET to expose portions of a substrate surface of the substrate. A source epitaxy and a drain epitaxy are formed from vertical epitaxial crystal growth on the exposed portions of the substrate surface after epitaxial deposition.

Claims

1. A method, comprising:

etching a fin of a fin-shaped field effect transistor (FinFET) to form a reduced fin;

laterally etching the reduced fin to form a fin channel including a first fin channel sidewall and a second fin channel sidewall opposing the first fin channel sidewall;

forming a first tunneling dielectric and a second tunneling dielectric on the first fin channel sidewall and the second fin channel sidewall, respectively, wherein each tunneling dielectric prevents lateral epitaxial crystal growth on the fin channel; and

etching an insulator layer disposed between the fin channel and a substrate of the FinFET to expose portions of a substrate surface of the substrate, wherein a source epitaxy and a drain epitaxy are formed from vertical epitaxial crystal growth on the exposed portions of the substrate surface.

2. The method of claim 1, wherein the fin, the substrate, the source epitaxy and the drain epitaxy comprise at least one semiconductor material.

3. The method of claim 2, wherein the fin and the substrate comprise silicon.

4. The method of claim 2, wherein the source epitaxy and the drain epitaxy comprise silicon germanium.

5. The method of claim 1, wherein the insulator layer and each tunneling dielectric comprise at least one dielectric material.

6. The method of claim 5, wherein the insulator layer comprises oxide.

7. The method of claim 5, wherein each tunneling dielectric comprises nitride.

8. The method of claim 1 further comprising:

forming a gate perpendicular to the fin channel;

forming a spacer including a first spacer sidewall and a second spacer sidewall opposing the first spacer sidewall; and

forming a dielectric layer disposed between the fin channel and the gate to separate the fin channel from the gate.

9. The method of claim 8, wherein:

forming the reduced fin comprises;

forming a first reduced fin sidewall and a second reduced fin sidewall opposing the first reduced fin sidewall; and

substantially aligning the first reduced fin sidewall and the second reduced fin sidewall with the first spacer sidewall and the second spacer sidewall, respectively.

10. The method of claim 8, wherein the fin channel is narrower than the gate.

11. The method of claim 1, wherein each tunneling dielectric is formed by one of thermal nitridation or plasma nitridation.

12. The method of claim 1, wherein each thin dielectric tunnel has a corresponding thickness that allows current to pass through it, thereby enabling the current to flow through the fin channel from the source epitaxy to the drain epitaxy.

13. The method of claim 12, wherein each thin dielectric tunnel has a corresponding thickness that is less than one nanometer.

14. The method of claim 8, wherein:

the reduced insulator layer includes a first reduced insulator layer sidewall and a second reduced insulator layer sidewall opposing the first reduced insulator layer sidewall; and

the first reduced insulator layer sidewall and the second reduced insulator layer sidewall are substantially aligned with the first spacer sidewall and the second spacer sidewall, respectively.