CMOS level shifter with reduced high voltage transistor count

• US 9,537,469 B2
• Filed: 11/06/2014
• Issued: 01/03/2017
• Est. Priority Date: 11/06/2013
• Status: Active Grant

• Current Assignee: Treehouse Design, Inc.
• Original Assignee: Treehouse Design, Inc.
• Inventors: Farooqi, Neaz, Noufer, Glenn E., Sandusky, Randall L.
• Primary Examiner(s): NGUYEN, LONG T
• Application Number:
  US15/034,814
• Publication Number:
  US 20160294370A1
• Time in Patent Office: 789 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356165 using additional transistors in the feedback circuit

Abstract

A digital level shifter adapted to shift an input signal from switching in a low voltage range, to an output switching in a high voltage range has a glitch generator configured to generate pulses at rising and falling transitions of the input signal. Glitch generator output triggers a multiple-level current source to a high current mode, operating in a low current mode at other times. The current source feeds a differential pair of high voltage transistors with a first transistor of the pair having a gate coupled to the input signal and a second transistor of the pair having a gate coupled to a complement of the input signal. An active load and buffer circuit receives current from the differential pair and drives the output accordingly.

Claims

1. A digital level shifter adapted to shift an input signal from switching between a low voltage and the low voltage less a first offset voltage, to an output switching between a high voltage and a voltage equal to the high voltage less a second offset voltage, the high voltage being greater than the low voltage, comprising:

a glitch generator configured to generate pulses at rising and falling transitions of the input signal;

a multiple-level current source configured to provide a high current during the pulses from the glitch generator, and a low current at other times;

a differential pair of high voltage transistors having sources coupled to the multiple-level current source, with a first transistor of the pair having a gate coupled to the input signal and a second transistor of the pair having a gate coupled to a complement of the input signal;

an active load and buffer circuit, the active load powered by the high voltage and configured to drive the output to the high voltage when the input signal has a first value, and to drive the output to the voltage equal to the high voltage less the second offset when the input signal has a second value.

2. The digital level shifter of claim 1 wherein the active load comprises cross-coupled latch transistors configured to increase a gain of the active load.

3. The digital level shifter of claim 1 wherein drains of the high voltage transistors are coupled to the active load.

4. The digital level shifter of claim 1, further comprising a first and second current mirror of high voltage transistors coupled to mirror currents derived from drain currents of the differential pair by a second active load, outputs of the first and second current mirror of high voltage transistors being coupled to drive the active load.

5. A method of shifting an input signal from a low level to a high level comprising:

providing a low level current to a differential pair of high voltage transistors, at least one transistor of the differential pair being coupled to the input signal;

detecting changes of the input signal, and, upon detecting changes of the input signal, providing a high level current to the differential pair of high voltage transistors; and

detecting a differential current from drains of the high voltage transistors, and deriving an output signal therefrom.

6. The method of claim 5, wherein the high level current is greater than 100 times the low level current.

7. A low-voltage to high-voltage level shifter comprising

a current source coupled to provide current to a source of a first high voltage transistor, and to a source of a second high voltage transistor;

a low voltage input signal coupled to a gate of the first high voltage transistor, and a complementary low voltage input signal coupled to a gate of the second high voltage transistor;

the drain of the first high voltage transistor being coupled to a drain of a first cross-coupled low-voltage transistor, the drain of the second high voltage transistor being coupled to a drain of a second cross-coupled low-voltage transistor;

wherein the gate of the first cross-coupled low-voltage transistor is coupled to the drain of the second high voltage transistor, and the gate of the second cross-coupled transistor is coupled to the drain of the first high voltage transistor;

where the low and high voltage transistors are selected from the group consisting of N-channel and P-channel MOS transistors;

wherein the current source is adapted to provide a first current to the sources of the high voltage transistors when the low voltage input signal is stable and to provide a second current greater than the first current when the low voltage input signal changes.

8. The level shifter of claim 7 further comprising an output buffer coupled to be driven to a first level when the drain of the first high voltage transistor carries greater current than the drain of the second high voltage transistor, and to a second level when the drain of the first high voltage transistor carries less current than the drain of the second high voltage transistor.