Flexible memory systems and methods

• US 9,538,038 B2
• Filed: 12/09/2013
• Issued: 01/03/2017
• Est. Priority Date: 06/10/2011
• Status: Active Grant

• Current Assignee: Teledyne FLIR LLC (Teledyne Technologies Incorporated)
• Original Assignee: FLIR Systems, Inc. (Teledyne Technologies Incorporated)
• Inventors: Sieh, Weilming, Dart, David W., Hgasten, Nicholas, Hoelter, Theodore R., Strandemar, Katrin, Boulanger, Pierre, Sharp, Barbara, Kurth, Eric A.
• Primary Examiner(s): Rao, Andy
• Assistant Examiner(s): Edwards, Tyler
• Application Number:
  US14/101,220
• Publication Number:
  US 20140098237A1
• Time in Patent Office: 1,121 Days
• US Class Current: 1/1
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: H04N 1/2137 with temporary storage before final recording, e.g. in a frame buffer
• CPC Class Codes: H04N 5/33 Transforming infrared radiation cameras or camera modules for generating image signals from infrared radiation H04N23/20; circuitry of SSIS for transforming infrared radiation into image signals H04N25/20

Abstract

Techniques are provided to implement line based processing of thermal images and a flexible memory system. In one example, individual lines of a thermal image frame may be provided to an image processing pipeline. Image processing operations may be performed on the individual lines in stages of the image processing pipeline. A memory system may be used to buffer the individual lines in the pipeline stages. In another example, a memory system may be used to send and receive data between various components without relying on a single shared bus. Data transfers may be performed between different components and different memories of the memory system using a switch fabric to route data over different buses. In another example, a memory system may support data transfers using different clocks of various components, without requiring the components and the memory system to all be synchronized to the same clock source.

Claims

1. A device comprising:

a plurality of components adapted to transfer thermal image data;

a plurality of buses connected to the components; and

a memory system connected to the components by the buses, the memory system comprising;

a plurality of memory buffers, each memory buffer comprising;

a memory block comprising a single interface adapted to support a single read or write operation at a time,

a plurality of ports, wherein each port is adapted to communicate with a corresponding one of the components over a corresponding one of the buses, and

a switch fabric block adapted to selectively couple the ports with the memory block through the single interface, and

a memory controller adapted to generate control signals to operate the switch fabric block to;

selectively couple a first one of the ports with the memory block to transfer the thermal image data between a first one of the components and the memory block through the single interface, and

selectively couple a second one of the ports with the memory block to transfer the thermal image data between a second one of the components and the memory block through the single interface.

2. The device of claim 1, wherein each memory buffer is adapted to store a different single line of a thermal image frame included in the thermal image data.

3. The device of claim 2, wherein each memory buffer is a pipeline register for a line based image processing pipeline used to process the thermal image frame.

4. The device of claim 1, wherein each port is adapted to receive a clock signal from the corresponding one of the components over the corresponding one of the buses, wherein the memory block is adapted to be synchronized by the clock signal received by the coupled port.

5. The device of claim 4, further comprising a clock switch adapted to switch between the clock signals to synchronize the memory block in a glitchless manner.

6. The device of claim 1, wherein the switch fabric block comprises a multiplexer adapted to select the ports based on the control signals.

7. The device of claim 1, wherein the memory controller is adapted to provide the control signals in accordance with a predetermined instruction sequence to transfer the thermal image data.

8. The device of claim 1, wherein:

a first subset of the components is connected to a first subset of the memory buffers by the buses, but is not connected to a second subset of the memory buffers by the buses; and

a second subset of the components is connected to the second subset of the memory buffers by the buses, but is not connected to the first subset of the memory buffers by the buses.

9. The device of claim 1, wherein:

the first one of the components is adapted to communicate with a first one of the memory buffers and a second one of the memory buffers;

the second one of the components is adapted to communicate with the first memory buffer but not the second memory buffer; and

the first component is adapted to read the thermal image data from the second memory buffer and write the thermal image data to the first memory buffer to share the thermal image data with the second component.

10. The device of claim 1, wherein the components comprise at least one of an application specific integrated circuit (ASIC), a general purpose processor, and/or a non-volatile memory block of the memory system, and wherein the memory block is a static random access memory (SRAM) block.

11. A method of operating a memory system and a plurality of components connected to the memory system by corresponding buses, the method comprising:

operating a switch fabric to selectively couple a first port of a memory buffer with a memory block of the memory buffer, wherein the memory block comprises a single interface adapted to support a single read or write operation at a time, wherein the memory buffer is part of the memory system;

transferring first thermal image data between a first one of the components and the memory block over a first one of the buses, through the first port, and through the single interface;

subsequently operating the switch fabric to selectively couple a second port of the memory buffer with the memory block; and

transferring second thermal image data between a second one of the components and the memory block over a second one of the buses, through the second port, and through the single interface.

12. The method of claim 11, further comprising storing in the memory buffer a single line of a thermal image frame included in the thermal image data.

13. The method of claim 12, wherein the memory buffer is a pipeline register for a line based image processing pipeline used to process the thermal image frame.

14. The method of claim 11, further comprising:

receiving a first clock signal from the first component over the first bus and at the first port;

receiving a second clock signal from the second component over the second bus and at the second port;

synchronizing the memory block by the first clock signal while the first port is coupled with the memory block; and

synchronizing the memory block by the second clock signal while the second port is coupled with the memory block.

15. The method of claim 14, further comprising switching between the first and second clock signals to synchronize the memory block in a glitchless manner.

16. The method of claim 11, further comprising receiving control signals at the memory buffer, wherein the operating steps are performed by a multiplexer of the switch fabric block to select the first or second ports.

17. The method of claim 16, further comprising providing the control signals from a memory controller of the memory system to select the first or second ports in accordance with a predetermined instruction sequence to transfer the thermal image data.

18. The method of claim 11, wherein:

the memory system comprises a plurality of memory buffers;

a first subset of the components is connected to a first subset of the memory buffers by the buses, but is not connected to a second subset of the memory buffers by the buses; and

a second subset of the components is connected to the second subset of the memory buffers by the buses, but is not connected to the first subset of the memory buffers by the buses.

19. The method of claim 11, wherein:

the memory buffer is a first memory buffer;

the first component is adapted to communicate with the first memory buffer and a second memory buffer;

the second component is adapted to communicate with the first memory buffer but not the second memory buffer; and

the method further comprises;

reading the thermal image data from the second memory buffer using the first component, and

writing the thermal image data to the first memory buffer using the first component to share the thermal image data with the second component.

20. The method of claim 11, wherein the components comprise at least one of an application specific integrated circuit (ASIC), a general purpose processor, and/or a non-volatile memory block of the memory system, and wherein the memory block is a static random access memory (SRAM) block.