Periodic signal measurement using statistical sampling
First Claim
1. A method for performing analysis of a periodic signal having an associated duty cycle that is generated in accordance with operations of at least one of a functional circuit and an embedded memory circuit, the method comprising:
- performing multiple sampling events during a test period according to a sample timing schedule determined by repeatedly detecting a recurring signal feature of a reference signal, wherein each sampling event of said multiple sampling events includes determining an asserted/de-asserted state of an associated signal phase of said periodic signal occurring at an associated sample time determined by detecting an associated said recurring signal feature, and wherein the reference signal has a reference frequency that is uncorrelated to the periodic signal such that each recurring signal feature of said reference signal coincides in time with a substantially random signal phase of said periodic signal, whereby a probability of detecting an asserted state during any given said sampling event is proportional to the associated duty cycle of the periodic signal;
generating a first count value such that said first count value only incrementally increases in response to each said sampling event occurring during said test period in which said periodic signal is in said asserted state; and
generating a second count value including a total number of said plurality of sampling events performed during said test period,wherein performing said multiple sampling events comprises performing a statistically significant number of said multiple sampling events during said test period such that a ratio of said first count value to said second count value at an end of said test period provides a statistically relevant measurement value of said associated duty cycle of the periodic signal.
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Abstract
A fully-digital probabilistic measurement methodology in which a periodic signal generated on an IC device is sampled multiple times during a test period, with the asserted/de-asserted state of the periodic signal determined during each sampling event. A statistically significant number of sampling events are executed according to a reference signal frequency that is uncorrelated to the IC'"'"'s system clock, whereby each successive sampling event involves detecting an essentially random associated phase of the periodic signal such that the probability of detecting an asserted state during any given sampling event is proportional to the duty cycle of the periodic signal. A first count value records the number of sampling events in which the periodic signal is asserted, and a second count value records the total number of sampling events performed, whereby a ratio of these two count values provides a statistical measurement of the periodic signal'"'"'s duty cycle.
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Citations
19 Claims
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1. A method for performing analysis of a periodic signal having an associated duty cycle that is generated in accordance with operations of at least one of a functional circuit and an embedded memory circuit, the method comprising:
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performing multiple sampling events during a test period according to a sample timing schedule determined by repeatedly detecting a recurring signal feature of a reference signal, wherein each sampling event of said multiple sampling events includes determining an asserted/de-asserted state of an associated signal phase of said periodic signal occurring at an associated sample time determined by detecting an associated said recurring signal feature, and wherein the reference signal has a reference frequency that is uncorrelated to the periodic signal such that each recurring signal feature of said reference signal coincides in time with a substantially random signal phase of said periodic signal, whereby a probability of detecting an asserted state during any given said sampling event is proportional to the associated duty cycle of the periodic signal; generating a first count value such that said first count value only incrementally increases in response to each said sampling event occurring during said test period in which said periodic signal is in said asserted state; and generating a second count value including a total number of said plurality of sampling events performed during said test period, wherein performing said multiple sampling events comprises performing a statistically significant number of said multiple sampling events during said test period such that a ratio of said first count value to said second count value at an end of said test period provides a statistically relevant measurement value of said associated duty cycle of the periodic signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An integrated circuit (IC) device comprising:
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at least one of a functional circuit and an embedded memory circuit fabricated on a semiconductor substrate and configured to operate in accordance with a system clock signal having a system clock frequency; and a periodic signal measurement circuit fabricated on the semiconductor substrate and configured to analyze, during a test period, a periodic signal having an associated duty cycle and is generated in accordance with operations of said at least one of said functional circuit and said embedded memory circuit, said periodic signal measurement circuit including; a reference signal generator configured to generate a reference signal such that a reference frequency of the reference signal is uncorrelated to the periodic signal; a sampling circuit configured to repeatedly detect a recurring signal feature of said reference signal, and to perform multiple sampling events at respective sample times determined by sequential detections of said recurring signal feature, wherein each sampling event of said multiple sampling events includes determining an asserted/de-asserted state of an associated signal phase of said periodic signal occurring at an associated sample time of said respective sample times determined by a detection of an associated recurring signal feature such that a probability of detecting an asserted state during any given said sampling event is proportional to the associated duty cycle of the periodic signal; a detection counter configured to generate a first count value such that said first count value only incrementally increases in response to each said sampling event occurring during said test period in which said periodic signal is determined to be in said asserted state; a sampling event counter configured to generate a second count value such that said second count value incrementally increases in response to every said sampling event occurring during said test period; and a control circuit configured to control said detection counter and said sampling event counter such that a statistically significant number of said multiple sampling events are performed during said test period such that a ratio of said first count value to said second count value at an end of said test period provides a statistically relevant measurement value of said associated duty cycle of the periodic signal. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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Specification