System and methods for performing embedded full-stripe write operations to a data volume with data elements distributed across multiple modules

• US 9,542,101 B2
• Filed: 09/22/2013
• Issued: 01/10/2017
• Est. Priority Date: 01/22/2013
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Simionescu, Horia, Baderdinni, Anant, Bert, Luca
• Primary Examiner(s): Schnee, Hal
• Assistant Examiner(s): GRULLON, FRANCISCO A
• Application Number:
  US14/033,474
• Publication Number:
  US 20140208024A1
• Time in Patent Office: 1,206 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 2211/1059 Parity-single bit-RAID5, i.e. RAID 5 implementations
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A data storage system and methods for managing data to be transferred between a host and a data volume distributed across solid state storage modules are disclosed. A storage controller couples the host to the data volume and manages data transfers to and from the logical volume. The storage controller receives a set of parameters that define how an array of blocks and chunks of buffered data will be distributed across solid state storage modules. The storage controller receives and buffers data to be stored and transfers the same when the capacity of the buffered data will fill a set of arranged stripes in the defined array in a single write operation.

Claims

1. A data storage system, comprising:

a cache memory; and

a controller comprising processing logic that is configurable to define and manage data transfers to and from at least one logical volume to be exposed to a host device, the data transfers as managed by the controller including data aligned for a single write operation to a stride in a defined array of N solid state storage modules, where N is a positive integer that is greater than or equal to 2, each stride comprising a set of two or more arranged stripes and being capable of being transferred by the controller to the N solid state storage modules in a single write operation, each stripe comprising data bits and parity bits generated from the data bits, the defined array having a specifically-defined layout in which the stripes are distributed across the N solid state storage modules in a manner dictated by the layout, wherein the data to be transferred by the controller is collected in the cache memory until the data present in the cache memory meets or exceeds the storage capacity of the stride, and wherein when the data present in the cache memory meets or exceeds the storage capacity of the stride, the controller causes the data present in the cache memory to be transferred to the N solid storage modules in a single write operation in accordance with the specifically-defined layout of the defined array.

2. The data storage system of claim 1, wherein the N solid states modules are coupled to the controller via dedicated interfaces.

3. The data storage system of claim 1, wherein the N solid state modules are integrated on a printed circuit.

4. The data storage system of claim 1, wherein the set of arranged stripes is spatially allocated across at least a portion of the N solid state storage modules, said at least two stripes being segmented in blocks and chunks, the controller directing the transfer of the data from cache memory to said at least a portion of the N solid state storage modules in a one-to-one manner with each chunk and a parity chunk being stored in a respective solid storage module, and wherein the blocks have a data storage capacity that is greater than the bandwidth of an I/O circuit pipeline that communicates digital data to and from the circuit elements that store the data in the solid state memory units.

5. The data storage system of claim 4, wherein the chunks have a data storage capacity that is equal to the bandwidth of the I/O circuit pipeline that communicates digital data to and from the circuit elements that store the data in the solid state memory units.

6. The data storage system of claim 5, wherein the set of arranged stripes is arranged in a sequential manner across the N solid state storage modules.

7. The data storage system of claim 5, wherein the set of arranged stripes is arranged in a planar manner across the N solid state storage modules.

8. The data storage system of claim 1, wherein the host includes executable code that when executed by a processor coupled to the host enable operating system level functions with data processed by the controller.

9. The data storage system of claim 1, wherein the host includes executable applications that operate in accordance with an input received via an interface, the executable applications, when executed by a processor coupled to the host, enable application level interaction with data processed by the controller.

10. The data storage system of claim 9, wherein the interface is a human-to-machine interface.

11. A method for processing data between a host and a data volume implemented by a controller, the method comprising:

defining a layout across a set of N solid state modules, the layout including multiple strides, each stride having at least two arranged stripes;

storing, in cache memory, data received from a host that is to be stored in a data volume in the set of N solid state modules;

determining, with the controller, when an amount of the data stored in the cache memory is equal to or exceeds the storage capacity of a stride having a set of stripes defined in the layout; and

when the amount of data stored in the cache memory is equal to or exceeds the storage capacity of the stride, transferring the data from the cache memory to the N solid state modules in a single write operation.

12. The method of claim 11, wherein the layout defines a data storage capacity of a block as a function of the bandwidth of an I/O circuit pipeline that communicates digital data to and from circuit elements that store the data in solid state memory units in the N solid state modules.

13. The method of claim 11, wherein the layout defines a data storage capacity of a chunk that is equal to the bandwidth of an I/O circuit pipeline that communicates digital data to and from circuit elements that store the data in solid state memory units in the N solid state modules.

14. The method of claim 11, wherein the set of arranged stripes is arranged in a sequential manner across the N solid state storage modules.

15. The method of claim 11, wherein the set of arranged stripes is arranged in a planar manner across the N solid state storage modules.

16. A non-transitory storage medium including a set of instructions, said set of instructions adapted to be executed by a storage controller to enable a method for performing embedded full-stripe write operations to a data volume distributed across multiple solid-state storage modules, the instructions comprising:

instructions for receiving, with a storage controller, a set of parameters that define a layout for distributing data across a set of N solid state storage modules, where N is a positive integer that is greater than or equal to 2, the layout defining multiple strides, each stride having a set of at least two stripes;

instructions for storing, in a cache memory coupled to the storage controller, data received from a host that is to be stored in the set of N solid state modules;

instructions for determining when an amount of data stored in the cache memory is equal to or exceeds the storage capacity of a stride defined by the layout; and

instructions for causing the controller to transfer the data stored in the cache memory to from the cache memory to the N solid state modules in a single write operation when a determination is made that the amount of data stored in the cache memory is equal to or exceeds the storage capacity of the stride defined by the layout.

17. The non-transitory storage medium of claim 16, wherein each stride is spatially distributed across less than all members of the set of N solid state modules the contents of which are filled in a single write operation by the storage controller.