Expositive flash memory control
First Claim
1. A flash memory device comprising:
- a flash storage having a plurality of storage locations disposed within structural elements hierarchically arranged such that a structural element at each hierarchical level above a lowest level enables access to a respective subset of structural elements at each lower hierarchical level; and
a memory controller that, upon receiving an incoming address value in association with a memory access command, generates a plurality of hierarchical sub-address values that correspond to groups of the structural elements at respective hierarchical levels, including generating at least one hierarchical sub-address, at least in part, through a modulo operation that returns a remainder of at least a portion of the incoming address value divided by a quantity of access-enabled structural elements at the respective hierarchical level to which the hierarchical sub-address corresponds, at least one of the hierarchical sub-address values being a virtual address.
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Accused Products
Abstract
This disclosure provides techniques of hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.
173 Citations
32 Claims
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1. A flash memory device comprising:
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a flash storage having a plurality of storage locations disposed within structural elements hierarchically arranged such that a structural element at each hierarchical level above a lowest level enables access to a respective subset of structural elements at each lower hierarchical level; and a memory controller that, upon receiving an incoming address value in association with a memory access command, generates a plurality of hierarchical sub-address values that correspond to groups of the structural elements at respective hierarchical levels, including generating at least one hierarchical sub-address, at least in part, through a modulo operation that returns a remainder of at least a portion of the incoming address value divided by a quantity of access-enabled structural elements at the respective hierarchical level to which the hierarchical sub-address corresponds, at least one of the hierarchical sub-address values being a virtual address. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A flash memory device comprising:
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a flash storage having a plurality of storage locations disposed within structural elements hierarchically arranged such that a structural element at each hierarchical level above a lowest level enables access to a respective subset of structural elements at each lower hierarchical level, wherein the lowest level of the hierarchy comprises independently programmable units of memory cells, and wherein a higher level of the hierarchy comprises flash memory dies; and a memory controller that, upon receiving an incoming address value in association with a memory access command, generates a plurality of hierarchical sub-address values that correspond to groups of the structural elements at respective hierarchical levels, including generating at least one hierarchical sub-address, at least in part, through a modulo operation that returns a remainder of at least a portion of the incoming address value divided by a quantity of access-enabled structural elements at the respective hierarchical level to which the hierarchical sub-address corresponds, at least one of the hierarchical sub-address values being a virtual address, and one of the hierarchical sub-addresses comprises a die address; and wherein the memory controller is further to generate a page address from each incoming address value a page address, in dependence on at least one remainder produced from generating the die address from the incoming address value. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A flash memory device comprising:
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a flash storage having a plurality of storage locations disposed within structural elements hierarchically arranged such that a structural element at each hierarchical level above a lowest level enables access to a respective subset of structural elements at each lower hierarchical level; a memory controller that, upon receiving an incoming address value in association with a memory access command, generates a plurality of hierarchical sub-address values that correspond to groups of the structural elements at respective hierarchical levels, including generating at least one hierarchical sub-address, at least in part, through a modulo operation that returns a remainder of at least a portion of the incoming address value divided by a quantity of access-enabled structural elements at the respective hierarchical level to which the hierarchical sub-address corresponds, at least one of the hierarchical sub-address values being a virtual address; and communications channels each coupling the memory controller with at least one flash memory die; wherein a first one of the hierarchical sub-addresses comprises a channel address, a second one of the hierarchical sub-addresses comprises die address, a third one of the hierarchical sub-addresses comprises an erasable unit address and a fourth one of the hierarchical sub-addresses comprises a page address. - View Dependent Claims (31, 32)
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Specification