Random number generator and method for generating random numbers

• US 9,542,157 B2
• Filed: 04/06/2015
• Issued: 01/10/2017
• Est. Priority Date: 04/11/2014
• Status: Active Grant

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Falk, Rainer, Fries, Steffen
• Primary Examiner(s): CHEN, SHIN HON
• Application Number:
  US14/679,099
• Publication Number:
  US 20150293748A1
• Time in Patent Office: 645 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 7/582 Pseudo-random number generators
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: H04L 9/0866 involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics
• CPC Class Codes: H04L 9/0869 involving random numbers or seeds
• CPC Class Codes: H04L 9/3234 involving additional secure or trusted devices, e.g. TPM, smartcard, USB or software token network architectures or network communication protocols for supporting authentication of entities using an additional device in a packet data network H04L63/0853

Abstract

A random number generator for generating random numbers using a solid-state memory is proposed. The random number generator includes a determination unit for determining management data stored in the solid-state memory and for managing the solid-state memory during operation. The random number generator also includes a computing unit for calculating a starting value on the basis of the determined management data. The random number generator also includes a generation unit for generating a random number on the basis of the calculated starting value.

Claims

1. A random number generator for generating random numbers, the random number generator comprising:

at least one microprocessor; and

a solid-state memory configured to, with the at least one microprocessor, cause the random number generator to at least perform;

determine management data stored in the solid-state memory and manage the solid-state memory during operation such that at least one defective memory cell of the solid-state memory is marked;

calculate a starting value using the at least one marked defective memory cell of the determined management data; and

generate a random number using the calculated starting value.

2. The random number generator as claimed in claim 1, wherein the management data comprise information relating to memory areas of the solid-state memory.

3. The random number generator as claimed in claim 2, wherein the information comprises one or more of the following:

(1) a degree of wear, (2) a counter of read, write, or read and write access operations, or (3) information relating to a shift of logical memory blocks to physical memory blocks.

4. The random number generator as claimed in claim 1, wherein the starting value is calculated using a cryptographic hash function.

5. The random number generator as claimed in claim 1, wherein the starting value is calculated using a symmetrical algorithm.

6. The random number generator as claimed in claim 1, wherein the starting value is calculated using the management data and at least one property of the solid-state memory.

7. The random number generator as claimed in claim 6, wherein the at least one property comprises device-specific parameters, access times to memory cells of the solid-state memory, or both the device-specific parameters and the access times to the memory cells of the solid-state memory.

8. The random number generator as claimed in claim 7, wherein the device-specific parameters comprise a serial number of the solid-state memory.

9. The random number generator as claimed in claim 1, wherein the starting value is calculated using the management data and a key, the key being determined by at least one property of the solid-state memory.

10. The random number generator as claimed in claim 1, wherein the solid-state memory, with the at least one microprocessor, cause the random number generator to further perform:

receive the management data from a controller.

11. The random number generator as claimed in claim 10, wherein the controller is arranged internally in the solid-state memory and is configured to manage the management data.

12. The random number generator as claimed in claim 11, wherein the controller is configured to control access to the solid-state memory using the generated random number.

13. The random number generator as claimed in claim 12, wherein the controller is configured to generate a key for encrypting or decrypting data stored in the solid-state memory using the generated random number.

14. The random number generator as claimed in claim 11, wherein the controller is configured to generate a key for encrypting or decrypting data stored in the solid-state memory using the generated random number.

15. The random number generator as claimed in claim 1, wherein the solid-state memory comprises a solid-state disk, an SD card, a USB storage device, a flash memory module, or a combination thereof.

16. The random number generator as claimed in claim 1, wherein the at least one defective memory cell is formed during production of the solid-state memory.

17. The random number generator as claimed in claim 1, wherein the at least one defective memory cell is formed during use of the solid-state memory.

18. A method for generating random numbers using a solid-state memory, the method comprising:

determining, by a microprocessor, management data stored in the solid-state memory for managing the solid-state memory during operation, wherein at least one defective memory cell of the solid-state memory is marked;

calculating, by the microprocessor, a starting value using the at least one marked defective memory cell of the determined management data; and

generating, by the microprocessor, a random number using the calculated starting value.

19. The method as claimed in claim 18, wherein the at least one defective memory cell is formed during production of the solid-state memory.

20. The method as claimed in claim 18, wherein the at least one defective memory cell is formed during use of the solid-state memory.