Data storage device and flash memory control method
First Claim
1. A data storage device, comprising:
- a flash memory, providing a storage space that is divided into a plurality of blocks with each block comprising a plurality of physical pages; and
a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory,wherein;
the microcontroller is configured to build a physical-to-logical address mapping table in the random access memory for a run-time write block between the blocks of the flash memory;
the microcontroller is further configured to allocate the random access memory to provide a collection and update area for logical-to-physical address mapping tables that correspond to logical addresses recorded into the physical-to-logical address mapping table; and
when recording a logical address corresponding to a new logical-to-physical address mapping table that has not appeared in the collection and update area into the physical-to-logical address mapping table, the microcontroller is further configured to collect the new logical-to-physical address mapping table into the collection and update area and perform an update of the new logical-to-physical address mapping table within the collection and update area.
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Accused Products
Abstract
A data storage device and a flash memory control method with high efficiency are disclosed. The random access memory of the data storage device is allocated to provide a collection and update area for logical-to-physical address mapping tables that correspond to logical addresses recorded into the physical-to-logical address mapping table. When recording a logical address corresponding to a new logical-to-physical address mapping table that has not appeared in the collection and update area into the physical-to-logical address mapping table, the microcontroller of the data storage device is configured to collect the new logical-to-physical address mapping table into the collection and update area and perform an update of the new logical-to-physical address mapping table within the collection and update area.
46 Citations
14 Claims
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1. A data storage device, comprising:
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a flash memory, providing a storage space that is divided into a plurality of blocks with each block comprising a plurality of physical pages; and a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory, wherein; the microcontroller is configured to build a physical-to-logical address mapping table in the random access memory for a run-time write block between the blocks of the flash memory; the microcontroller is further configured to allocate the random access memory to provide a collection and update area for logical-to-physical address mapping tables that correspond to logical addresses recorded into the physical-to-logical address mapping table; and when recording a logical address corresponding to a new logical-to-physical address mapping table that has not appeared in the collection and update area into the physical-to-logical address mapping table, the microcontroller is further configured to collect the new logical-to-physical address mapping table into the collection and update area and perform an update of the new logical-to-physical address mapping table within the collection and update area. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A flash memory control method, comprising:
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providing a random access memory for a flash memory, the flash memory providing a storage space that is divided into a plurality of blocks with each block comprising a plurality of pages; building a physical-to-logical address mapping table in the random access memory for a run-time write block between the blocks of the flash memory; and allocating the random access memory to provide a collection and update area for logical-to-physical address mapping tables that correspond to logical addresses recorded in the physical-to-logical address mapping table, wherein when recording a logical address corresponding to a new logical-to-physical address mapping table that has not appeared in the collection and update area into the physical-to-logical address mapping table, the new logical-to-physical address mapping table is collected into the collection and update area and an update of the new logical-to-physical address mapping table is performed within the collection and update area. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification