Non-volatile memory cell and non-volatile memory device

• US 9,543,006 B2
• Filed: 10/06/2015
• Issued: 01/10/2017
• Est. Priority Date: 05/25/2015
• Status: Active Grant

• Current Assignee: Alto Memory Technology Corporation, Jiangsu Advanced Memory Technology Co., Ltd.
• Original Assignee: Being Advanced Memory Taiwan Limited, Ningbo Advanced Memory Technology Corp.
• Inventors: Wu, Jui-Jen, Chang, Jia-Hwang, Huang, Sheng-Tsai, Jien, Fan-Yi
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Techane, Muna A
• Application Number:
  US14/875,708
• Publication Number:
  US 20160351257A1
• Time in Patent Office: 462 Days
• Field of Search: 365/163
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes

Abstract

A non-volatile memory cell and a non-volatile memory device are provided. The non-volatile memory cell includes a latch structure, a first read/write circuit, a first memristor, a second read/write circuit and a second memristor. The first read/write circuit controls a writing operation of the first memristor. The second read/write circuit controls a writing operation of the second memristor. When a restore operation is performed, the data in the latch structure is restored by using the resistance difference between the first memristor and the second memristor. The non-volatile device of the invention combines the advantages of fast memory unit and non-volatile memory, and it may work at a high speed and retain data when powered off.

Claims

1. A non-volatile memory cell comprising:

a latch structure having a storage node and an inverted storage node, configured to store a pair of bits when the non-volatile memory cell is powered by a working voltage, wherein the latch structure is electrically coupled to a reading word line;

a first read/write circuit, electrically coupled to a bit line, a first control line and the latch structure;

a second read/write circuit, electrically coupled to an inverted bit line, the first control line and the latch structure;

a first memristor, directly connected to the first read/write circuit and a second control line; and

a second memristor, directly connected to the second read/write circuit and the second control line,

wherein the first read/write circuit comprises a fifth transistor and a sixth transistor, and the second read/write circuit comprises a seventh transistor and an eighth transistor;

each of the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor has a first terminal, a second terminal and a control terminal;

the second terminal of the fifth transistor is coupled to a system ground, and the control terminal of the fifth transistor is coupled to the first control line;

the second terminal of the sixth transistor is coupled to the first memristor and the control terminal of the sixth transistor is coupled to the bit line;

the first terminal the fifth transistor is connected to the first terminal of the sixth transistor, and is electrically coupled to the latch structure;

the second terminal of the seventh transistor is coupled to the system ground and the control terminal of the seventh transistor is coupled to the first control line;

the second terminal of the eighth transistor is coupled to the second memristor, and the control terminal of the eighth transistor is coupled to the inverted bit line; and

the first terminal of the seventh transistor is connected to the first terminal of the eighth transistor, and is electrically coupled to the latch structure;

wherein when the non-volatile memory cell is powered off, the first memristor and the second memristor are configured to store the pair of bits,

wherein when a voltage of the reading word line is at the working voltage, the bit line, the first control line and the second control line control the first read/write circuit to write data from the storage node into the first memristor, or read data from the first memristor into the storage node, and the inverted bit line, the first control line and the second control line control the second read/write circuit to write data from the inverted storage node into the second memristor, or read data from the second memristor to the inverted storage node.

2. The non-volatile memory cell of claim 1, wherein the latch structure comprises:

a first inverter having an output terminal and an input terminal; and

a second inverter having an output terminal and an input terminal,

wherein the output terminal of the first inverter is coupled to the input terminal of the second inverter, and the output terminal of the second inverter is coupled to the input terminal the first inverter to form cross coupling,

wherein the output terminal of the first inverter is the storage node of the latch structure, and the output terminal of the second inverter is the inverted storage node of the latch structure.

3. The non-volatile memory cell of claim 2, wherein the first inverter comprises a first transistor and a second transistor, and the second inverter comprises a third transistor and a fourth transistor,

wherein each of the first transistor, the second transistor, the third transistor and the fourth transistor has a first terminal, second terminal and a control terminal,

wherein the second terminal of the first transistor is connected to the first terminal of the second transistor, and is electrically coupled to the output terminal of the first inverter;

the control terminal of the first transistor is connected to the control terminal of the second transistor, and is electrically coupled to the input terminal of the first inverter; and

the first terminal of the first transistor is electrically coupled to the reading word line,

wherein the second terminal of the third transistor is connected to the first terminal of the fourth transistor, and is electrically coupled to the output terminal of the second inverter;

the control terminal of the third transistor is connected to the control terminal of the fourth transistor, and is electrically coupled to the input terminal of the second inverter; and

the first terminal of the third transistor is electrically coupled to the reading word line.

4. The non-volatile memory cell of claim 1, wherein the first memristor has a first resistance after a writing operation is performed thereon, and the second memristor has a second resistance after the writing operation is performed thereon.

5. The non-volatile memory cell of claim 4, wherein the first memristor and the second memristor comprise a phase-change memory.

6. The non-volatile memory cell of claim 4, wherein,

when the non-volatile memory cell performs a restore operation to read non-volatile data, the bit line and the inverted bit line turn on the sixth transistor and the eighth transistor;

the first control line keeps at a low voltage to turn off the fifth transistor and the seventh transistor;

the reading word line is raised from the low voltage to the working voltage to transiently raise a voltage of the storage node of the first inverter and a voltage of the inverted storage node of the second inverter; and

accordingly,

a voltage of the storage node and a voltage of the inverted storage node are respectively pushed to a high level and a low level due to a resistance difference between the first resistance and the second resistance.

7. The non-volatile memory cell of claim 4, wherein,

when the writing operation is performed on the first memristor, the reading word line is set to a low voltage;

the first control line is set to a high voltage to turn on the fifth transistor;

the bit line is set to the high voltage to turn on the sixth transistor; and

the second control line inputs a first writing pulse into the first memristor according to the bit in the storage node so as to set the first resistance.

8. The non-volatile memory cell of claim 4, wherein,

when the writing operation is performed on the second memristor, the reading word line is set to a low voltage;

the first control line is set to a high voltage to turn on the seventh transistor;

the inverted bit line is set to the high voltage to turn on the eighth transistor; and

the second control line inputs a second writing pulse into the second memristor according to the bit in the inverted storage node so as to set the second resistance.

9. A non-volatile memory device comprising:

a plurality of non-volatile memory cells of claim 1, wherein each of the non-volatile memory cells is configured to save a bit, and is coupled to a respective reading word line, a respective bit line, a respective inverted bit line, a respective first control line, a respective second control line and a respective system ground.