Pulse output circuit, shift register, and display device
First Claim
Patent Images
1. A display device comprising:
- a pixel portion provided on a substrate;
a driver circuit provided on the substrate,wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,wherein a gate of the first transistor is electrically connected to a gate of the third transistor,wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the third transistor,wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor through no transistor,wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the fourth transistor through no transistor,wherein the gate of the first transistor is arranged so that at least a first signal is input,wherein the gate of the second transistor is arranged so that at least a second signal is input,wherein the other of the source and the drain of the fourth transistor is arranged so that at least a first potential and a second potential are switched and supplied, andwherein the one of a source and a drain of the third transistor is arranged to output at least a third signal to the pixel portion.
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Abstract
In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.
85 Citations
22 Claims
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1. A display device comprising:
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a pixel portion provided on a substrate; a driver circuit provided on the substrate, wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein a gate of the first transistor is electrically connected to a gate of the third transistor, wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the third transistor, wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor through no transistor, wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the fourth transistor through no transistor, wherein the gate of the first transistor is arranged so that at least a first signal is input, wherein the gate of the second transistor is arranged so that at least a second signal is input, wherein the other of the source and the drain of the fourth transistor is arranged so that at least a first potential and a second potential are switched and supplied, and wherein the one of a source and a drain of the third transistor is arranged to output at least a third signal to the pixel portion. - View Dependent Claims (5, 7, 8, 17)
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2. A display device comprising:
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a pixel portion provided on a substrate; a driver circuit provided on the substrate, wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, wherein at least one of the first transistor to the fifth transistor comprises an oxide semiconductor layer comprises a channel formation region, wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein a gate of the first transistor is electrically connected to a gate of the third transistor, wherein the other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the third transistor, wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the second transistor through no transistor, wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the fourth transistor through no transistor, wherein the gate of the first transistor is arranged so that at least a first signal is input, wherein the gate of the second transistor is arranged so that at least a second signal is input, wherein the other of the source and the drain of the fourth transistor is arranged so that at least a first potential and a second potential are switched and supplied, and wherein the one of a source and a drain of the third transistor is arranged to output at least a third signal to the pixel portion. - View Dependent Claims (3, 4, 6, 18)
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9. A shift register comprising:
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a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, wherein each of the first transistor to the fifth transistor is an n-channel transistor, wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor, wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor, wherein a gate of the first transistor is directly connected to a gate of the third transistor, wherein the other of the source and the drain of the first transistor is directly connected to the other of the source and the drain of the third transistor, wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the second transistor, wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the fourth transistor, wherein the gate of the first transistor is arranged so that at least a first signal is input, wherein the gate of the second transistor is arranged so that at least a second signal is input, and wherein the other of the source and the drain of the fourth transistor is arranged so that at least a first potential and a second potential are switched and supplied. - View Dependent Claims (19)
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10. A shift register comprising:
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a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, wherein each of the first transistor to the fifth transistor is an n-channel transistor, wherein at least one of the first transistor to the fifth transistor comprises an oxide semiconductor layer comprises a channel formation region, wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor, wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor, wherein a gate of the first transistor is directly connected to a gate of the third transistor, wherein the other of the source and the drain of the first transistor is directly connected to the other of the source and the drain of the third transistor, wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the second transistor, wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the fourth transistor, wherein the gate of the first transistor is arranged so that at least a first signal is input, wherein the gate of the second transistor is arranged so that at least a second signal is input, and wherein the other of the source and the drain of the fourth transistor is arranged so that at least a first potential and a second potential are switched and supplied. - View Dependent Claims (11, 12, 20)
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13. A display device comprising:
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a pixel portion; and a driver circuit, wherein the pixel portion and the driver circuit are provided on the same substrate, wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, wherein each of the first transistor to the fifth transistor is an n-channel transistor, wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor, wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor, wherein a gate of the first transistor is directly connected to a gate of the third transistor, wherein the other of the source and the drain of the first transistor is directly connected to the other of the source and the drain of the third transistor, wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the second transistor, wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the fourth transistor, wherein the gate of the first transistor is arranged so that at least a first signal is input, wherein the gate of the second transistor is arranged so that at least a second signal is input, and wherein the other of the source and the drain of the fourth transistor is arranged so that at least a first potential and a second potential are switched and supplied. - View Dependent Claims (21)
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14. A display device comprising:
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a pixel portion; and a driver circuit, wherein the pixel portion and the driver circuit are provided on the same substrate, wherein the driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, wherein each of the first transistor to the fifth transistor is an n-channel transistor, wherein at least one of the first transistor to the fifth transistor comprises an oxide semiconductor layer comprises a channel formation region, wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor, wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor, wherein a gate of the first transistor is directly connected to a gate of the third transistor, wherein the other of the source and the drain of the first transistor is directly connected to the other of the source and the drain of the third transistor, wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the second transistor, wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the fourth transistor, wherein the gate of the first transistor is arranged so that at least a first signal is input, wherein the gate of the second transistor is arranged so that at least a second signal is input, wherein the other of the source and the drain of the fourth transistor is arranged so that at least a first potential and a second potential are switched and supplied, and wherein the one of a source and a drain of the third transistor is arranged to output at least a third signal to the pixel portion. - View Dependent Claims (15, 16, 22)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsAmano, Seiko, Miyake, Hiroyuki
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Primary Examiner(s)Olson, Jason
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Assistant Examiner(s)NEUPANE, KRISHNA P.
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Application NumberUS14/831,939Publication NumberTime in Patent Office508 DaysField of SearchNoneUS Class Current1/1CPC Class CodesG06F 1/3265 Power saving in display deviceG06F 3/038 Control and interface arran...G09G 2300/0809 Several active elements per...G09G 2300/0871 with level shiftingG09G 2310/0205 Simultaneous scanning of se...G09G 2310/0248 Precharge or discharge of c...G09G 2310/0286 Details of a shift register...G09G 2310/08 Details of timing specific ...G09G 2320/0247 Flicker reduction other tha...G09G 2330/021 Power management, e.g. powe...G09G 3/3266 Details of drivers for scan...G09G 3/3677 suitable for active matrice...G09G 5/008 Clock recoveryG11C 19/28 using semiconductor element...H01L 27/124 with a particular compositi...
