Recess technique to embed flash memory in SOI technology

• US 9,543,153 B2
• Filed: 07/16/2014
• Issued: 01/10/2017
• Est. Priority Date: 07/16/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chuang, Harry-Hak-Lay, Wu, Wei Cheng, You, Kai-Shyang
• Primary Examiner(s): BERNSTEIN, ALLISON
• Application Number:
  US14/332,556
• Publication Number:
  US 20160020219A1
• Time in Patent Office: 909 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/28017 the insulator being formed after the semiconductor body, the semiconductor being silicon
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

An integrated circuit arranged on a silicon-on-insulator (SOI) substrate region is provided. The SOI substrate region is made up of a handle wafer region, an oxide layer arranged over the handle wafer region, and a silicon layer arranged over the oxide layer. A recess extends downward from an upper surface of the silicon layer and terminates in the handle wafer region, thereby defining a recessed handle wafer surface and sidewalls extending upwardly from the recessed handle wafer surface to meet the upper surface of the silicon layer. A first semiconductor device is disposed on the recessed handle wafer surface. A second semiconductor device is disposed on the upper surface of the silicon layer.

Claims

1. An integrated circuit (IC) comprising:

a semiconductor on-insulator (SOI) substrate region made up of a handle substrate region, an insulating layer arranged over the handle substrate region, and a semiconductor layer arranged over the insulating layer;

a recess extending downward from an upper surface of the semiconductor layer and terminating in the handle substrate region, thereby defining a recessed handle substrate surface and sidewalls extending upwardly from the recessed handle substrate surface to meet the upper surface of the semiconductor layer;

a first semiconductor device disposed on the recessed handle substrate surface, the first semiconductor device including a first gate having a lowermost gate surface which is arranged at a first height below a second height of a lowermost surface of the insulating layer; and

a second semiconductor device disposed on the upper surface of the semiconductor layer.

2. The IC of claim 1, the first gate having a first gate top surface and wherein the second semiconductor device includes a second gate having a second gate top surface, wherein the first gate top surface is co-planar with the second gate top surface.

3. The IC of claim 1, further comprising:

a dielectric spacer arranged on the sidewalls of the recess and extending vertically from over the recessed handle substrate surface past the insulating layer and alongside the semiconductor layer.

4. The IC of claim 3, wherein a lowermost surface of the dielectric spacer directly contacts the recessed handle substrate surface and an uppermost portion of the dielectric spacer corresponds to the upper surface of the semiconductor layer.

5. The IC of claim 1, wherein the first semiconductor device is a non-volatile memory device and the second semiconductor device is a high-k metal gate device.

6. The IC of claim 5, wherein the non-volatile memory (NVM) device comprises:

a pair of NVM source/drain regions spaced apart from one another in the handle substrate;

a select gate (SG) disposed over the recessed handle substrate surface between the pair of NVM source/drain regions;

a memory gate (MG) disposed between a SG sidewall and one of the NVM source/drain regions of the pair; and

a charge trapping layer arranged between neighboring sidewalls of the MG and the SG and extending under the MG to separate the MG from the recessed handle substrate surface.

7. The IC of claim 5, wherein the high-k metal gate (HKMG) device comprises:

a pair of HKMG source/drain regions spaced apart from one another in the semiconductor layer; and

a metal gate disposed over the semiconductor layer and arranged between the pair of HKMG source/drain regions.

8. The IC of claim 7, wherein the non-volatile memory (NVM) device comprises:

a pair of NVM source/drain regions spaced apart from one another in the handle substrate;

a select gate (SG) disposed over the recessed handle substrate surface between the pair of NVM source/drain regions;

a memory gate (MG) disposed between a SG sidewall and one of the NVM source/drain regions of the pair; and

a charge trapping layer arranged between neighboring sidewalls of the MG and the SG and extending under the MG to separate the MG from the recessed handle substrate surface.

9. The IC of claim 8, wherein a top surface of the metal gate of the HKMG device is co-planar with a top surface of the SG or MG of the NVM device.

10. The IC of claim 8, wherein the NVM source/drain regions have a first implant depth and the HKMG source/drain regions have a second implant depth that is greater than the first implant depth.

11. The IC of claim 10, wherein the first implant depth, as measured between the recessed surface and a lower portion of the NVM source/drain regions, is greater than a thickness of the semiconductor layer, as measured between the upper surface of the semiconductor layer and an uppermost surface of the insulating layer.

12. The IC of claim 1, wherein the first semiconductor device comprises:

a pair of non-volatile memory (NVM) source/drain regions spaced apart from one another in the handle substrate region;

a select gate (SG) disposed over the recessed handle substrate surface between the pair of NVM source/drain regions;

a memory gate (MG) disposed between a SG sidewall and one of the NVM source/drain regions of the pair; and

a charge trapping layer arranged between neighboring sidewalls of the MG and the SG and extending under the MG to separate the MG from the recessed handle substrate surface.

13. The IC of claim 12, wherein a lowermost surface of the SG is arranged at a first height which is below a second height of a lowermost surface of the insulating layer.

14. The IC of claim 12, wherein at least a portion of the charge trapping layer is arranged at a first height which is below a second height of a lowermost surface of the insulating layer.

15. An integrated circuit (IC) comprising:

a semiconductor on-insulator (SOI) substrate region made up of a handle substrate region, an insulating layer arranged over the handle substrate region, and a semiconductor layer arranged over the insulating layer;

a recess extending downward from an upper surface of the semiconductor layer and terminating in the handle substrate region, thereby defining a recessed handle substrate surface and sidewalls extending upwardly from the recessed handle substrate surface to meet the upper surface of the semiconductor layer; and

a semiconductor device including a gate electrode having a lowermost gate surface which is arranged at a first height below a second height of a lowermost surface of the insulating layer;

wherein the recessed handle substrate surface corresponds to the semiconductor device and a memory region where an array of memory cells are arranged and wherein the upper surface of the semiconductor layer corresponds to a logic region where a memory array control circuit is arranged.

16. The IC of claim 15, wherein the memory cells are non-volatile memory cells and the memory array control circuit includes a high-k metal gate device.

17. The IC of claim 15, wherein a memory cell includes:

a select gate (SG) and a memory gate (MG) that each comprise poly silicon or metal;

a charge trapping layer separating the SG and MG, the charge trapping layer comprising;

an oxide-nitride-oxide (ONO) layer;

or

an arrangement of substantially spherical silicon nanocrystals arranged between a tunnel oxide layer and a control oxide layer.

18. The IC of claim 15, wherein the recess has a depth ranging from approximately 30 nm to 1000 nm.

19. The IC of claim 15, further comprising:

a dielectric spacer arranged on the sidewalls of the recess and extending vertically from over the recessed handle substrate surface past the insulating layer and alongside the semiconductor layer, wherein the spacer comprises a continuous nitride structure or a multi layer nitride-oxide-nitride (NON) structure.

20. An integrated circuit (IC) comprising:

a semiconductor-on-insulator (SOI) substrate region made up of a handle substrate region, an insulating layer arranged over the handle substrate region, and a semiconductor layer arranged over the insulating layer;

a recess extending downward from an uppermost surface of the semiconductor layer and terminating in the handle substrate region, thereby defining a recessed handle substrate surface and inner sidewalls extending upwardly from the recessed handle substrate surface to meet the uppermost surface of the semiconductor layer;

a first semiconductor device disposed on the recessed handle substrate surface the first semiconductor device including a first gate having a lowermost gate surface which is arranged at a first height below a second height of a lowermost surface of the insulating layer;

a second semiconductor device disposed on the upper surface of the semiconductor layer; and

a dielectric spacer arranged on the inner sidewalls and extending vertically from over the recessed handle substrate surface past the insulating layer and alongside the semiconductor layer, wherein a lowermost surface of the dielectric spacer directly contacts the recessed handle substrate surface, and wherein an uppermost portion of the dielectric spacer corresponds to the uppermost surface of the semiconductor layer.