Semiconductor package and method therefor

• US 9,543,235 B2
• Filed: 10/05/2015
• Issued: 01/10/2017
• Est. Priority Date: 10/24/2013
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Jeon, Hyung Il, Chung, Ji Young, Kim, Byong Jin, Park, In Bae, Bae, Jae Min, Park, No Sun
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US14/875,672
• Publication Number:
  US 20160118319A1
• Time in Patent Office: 463 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13014 being circular or elliptic
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13138 the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16013 the bump connector being larger than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/16258 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/81815 Reflow soldering
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49572 consisting of thin flexible metallic tape with or without a film carrier H01L23/49503 - H01L23/49568 and H01L23/49575 - H01L23/49579 take precedence
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

In one embodiment, an electronic package structure includes a lead having a first width. An electronic chip having a conductive bump on a major surface, the conductive bump has a second width greater than the first width. The conductive bump is attached to the lead such that a portion of the conductive bump extends to at least partially surround a side surface of the lead. A molding compound resin encapsulates the electronic chip, the conductive bump, and at least a portion of the lead. The lead is configured so strengthen the joining force between the lead and conductive bump.

Claims

1. A semiconductor package comprising:

a lead;

a semiconductor chip having a conductive bump disposed adjacent and overlapping a major surface of the semiconductor chip, wherein the major surface overlaps and faces the lead, and wherein the conductive bump is attached to the lead; and

an encapsulating layer sealing the semiconductor chip, at least a portion of the lead, and the conductive bump, wherein a portion of the conductive bump extends beyond an upper surface of the lead and at least partially surrounds a surface area of a portion of the lead, and wherein the lead is at least partially exposed to the outside of the encapsulating layer.

2. The semiconductor package of claim 1, wherein the lead comprises a bond finger and a land portion, and wherein the bond finger extends laterally away from the land portion, and wherein the conductive bump is attached to one of the bond finger or the land portion.

3. The semiconductor package of claim 1, wherein the conductive bump comprises a conductive pillar and a solder portion disposed on an outer tip portion of the conductive pillar.

4. The semiconductor package of claim 3, wherein the conductive pillar comprises copper.

5. The semiconductor package of claim 1, wherein the conductive bump completely surrounds the surface area of the portion of the lead.

6. The semiconductor package of claim 1, wherein at least a portion of the surface area comprises a concave portion.

7. The semiconductor package of claim 1, wherein the lead has concave portions on opposing side surfaces in cross-sectional view.

8. The semiconductor package of claim 7 further comprising a dimple in a major surface of the lead, wherein the dimple is disposed between the concave portions.

9. The semiconductor package of claim 1, wherein a portion of the lead where the conductive bump is attached comprises a narrow neck, which has a width smaller than another width of the lead.

10. The semiconductor package of claim 1 further comprising a dimple in a major surface of the lead, at least a portion of the conductive bump disposed within the dimple.

11. The semiconductor package of claim 1, wherein a width of the conductive bump is larger than a width of the lead, and wherein the semiconductor package has a bump-to-lead width ratio of about 2 or more.

12. A semiconductor package structure comprising:

a lead having side surfaces, wherein at least one side surface has a concave portion;

a semiconductor chip having a conductive bump on a major surface, wherein the conductive bump is attached to the lead, and wherein a portion of the conductive bump extends to at least partially surround the concave portion of the lead; and

an encapsulating layer configured to cover the semiconductor chip, the conductive bump, and at least a portion of the lead.

13. The structure of claim 12, wherein:

the lead has a first width and the conductive bump has a second width greater than the first width;

another portion of the lead is exposed in the encapsulating layer;

two opposing side surfaces of the lead have concave portions in cross-sectional view;

the conductive bump comprises a conductive pillar having a solder portion disposed on a distal tip of the conductive pillar; and

the solder portion extends to at least partially cover the two opposing sides surface of the lead.

14. The structure of claim 12 further comprising a dimple in a major surface of the lead, wherein a portion of the conductive bump is disposed within the dimple.

15. The structure of claim 12, wherein the portion of the conductive bump completely surrounds a portion of the lead.

16. The structure of claim 12, wherein

the lead has a first width and the conductive bump has a second width greater than the first width;

and

the lead further comprises a narrow neck portion, the narrow neck portion having the first width, and wherein the lead has a third width greater than the first width.

17. The structure of claim 12, wherein the lead has a first width and the conductive bump has a second width greater than the first width, and wherein the second width to first width ratio is 2 or more.

18. A semiconductor package comprising:

a lead frame comprising a first lead;

a semiconductor chip having a conductive bump disposed adjacent and overlapping a major surface of the semiconductor chip, wherein the major surface overlaps and faces the lead, and wherein the conductive bump is coupled to the first lead, and wherein a portion of the conductive bump extends to at least partially surround side surfaces of the lead; and

a molded encapsulating layer covering the semiconductor chip, the conductive bump, and at least portions of the lead frame, wherein a portion of the first lead is exposed to the outside of the molded encapsulating layer.

19. The semiconductor package of claim 18, wherein:

the first lead comprises a first width;

the conductive bump has a second width greater than the first width;

the second width to first width ratio is greater than or equal to 2; and

the first lead comprises one or more of a concave portion on a side surface of lead, a narrow neck portion, or a dimple in an upper surface of the lead.

20. The semiconductor package of claim 18, wherein:

the conductive bump comprises a conductive pillar having a solder portion on an end surface of the conductive pillar;

the lead frame further comprises a ground pad; and

the conductive pillar comprises copper.