Surface-mount electronic component

• US 9,543,247 B1
• Filed: 02/23/2016
• Issued: 01/10/2017
• Est. Priority Date: 08/31/2015
• Status: Active Grant

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Ory, Olivier
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US15/051,158
• Time in Patent Office: 322 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0203 Making porous regions on the surface
• CPC Class Codes: H01L 21/302 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• CPC Class Codes: H01L 21/3043 Making grooves, e.g. cutting
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/0556 : Disposition
• CPC Class Codes: H01L 2224/05571 : the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05582 : Two-layer coating
• CPC Class Codes: H01L 2224/05611 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 29/16 : including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

A surface-mount chip is formed by a silicon substrate having a front surface and a side. The chip includes a metallization intended to be soldered to an external device. The metallization has a first portion covering at least a portion of the front surface of the substrate and a second portion covering at least a portion of the side of the substrate. A porous silicon region is included in the substrate to separating the second portion of the metallization from the rest of the substrate.

Claims

1. A surface-mount integrated circuit chip, comprising:

a substrate having a front surface and a side;

at least one metallization configured to be soldered to an external device, said at least one metallization comprising a first portion covering at least a portion of the front surface of the substrate and a second portion covering at least a portion of the side of the substrate; and

a porous silicon region included in the substrate and separating the second portion of the metallization from a remainder of the substrate.

2. The chip of claim 1, wherein the second portion of the at least one metallization is arranged in a groove located on the side of the substrate.

3. The chip of claim 1, further comprising:

an active area formed inside and on top of the remainder of the substrate and containing an electronic circuit; and

at least one contact region connected to the electronic circuit and located on the front surface of the substrate,

wherein the first portion of the at least one metallization is connected to the at least one contact region.

4. The chip of claim 1, wherein an insulating layer is arranged between the front surface of the substrate and the first portion of the at least one metallization.

5. The chip of claim 4, wherein the porous silicon region is in contact with the insulating layer in an overlap area.

6. An integrated circuit chip, comprising:

a semiconductor substrate including an active area with circuits;

a metal contact over the semiconductor substrate and in electrical connection with the circuits of the active area;

a porous silicon region of the semiconductor substrate along a side edge of the semiconductor substrate; and

a metal layer having a first portion in contact with the metal contact and having a second portion extending from the first portion onto the side edge of the semiconductor substrate and in contact with the porous silicon region.

7. The chip of claim 6, further comprising an insulating layer on top of the semiconductor substrate and surrounding the metal contact, wherein said first portion of the metal layer extends over the insulating layer.

8. The chip of claim 7, wherein a portion of the porous silicon region extends under a peripheral edge of the insulating layer.