Pixel sensor cell including light shield

• US 9,543,356 B2
• Filed: 08/10/2009
• Issued: 01/10/2017
• Est. Priority Date: 03/10/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Rassel, Richard, Gambino, Jeffrey P., Jaffe, Mark D., Ellis-Monaghan, John
• Primary Examiner(s): Li, Meiya
• Application Number:
  US12/538,194
• Publication Number:
  US 20100230729A1
• Time in Patent Office: 2,710 Days
• Field of Search: 257/228, 257/292, 257/435, 257/E27.133, 257/E27.15, 257/E31.122, 257/E21.211, 257/447, 257/460, 438/69
• US Class Current: 1/1
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within the pixel sensor cells. In a first particular generalized embodiment, a light shielding layer is located and formed interposed between a first semiconductor layer that includes a photoactive region and a second semiconductor layer that includes the at least a second transistor, or a floating diffusion, that is shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of a floating diffusion, and located shielded in a dielectric isolated metallization stack over a carrier substrate.

Claims

1. A pixel sensor cell comprising:

a photoactive region located within a first semiconductor layer, wherein the first semiconductor layer is located a second semiconductor layer;

a transistor located partially within the second semiconductor layer, wherein the second semiconductor layer is located a carrier substrate;

a light blocking layer located interposed between the first semiconductor layer and the second semiconductor layer and shielding the transistor from back side illumination; and

a contact region comprised of a semiconductor material extending through the light blocking layer, wherein the contact region contacts the first semiconductor layer and the second semiconductor layer.

2. The pixel sensor cell of claim 1, further comprising a first transistor located within the first semiconductor layer and not shielded by the light blocking layer.

3. The pixel sensor cell of claim 2, wherein the light blocking layer comprises a gate for the first transistor.

4. The pixel sensor cell of claim 1, further comprising a floating diffusion region that is located within the second semiconductor layer and shielded by the light blocking layer.

5. The pixel sensor cell of claim 1,

wherein the contact region comprises a first p-dopant concentration from about 1×

10¹⁹ to about 5×

10²⁰ p-dopant atoms per cubic centimeter,

wherein the photoactive region comprises an n-dopant concentration from about 1×

10¹⁵ to about 1×

10¹⁷ n-dopant atoms per cubic centimeter, and

wherein the first semiconductor layer comprises a second p-dopant concentration from about 1×

10¹³ to about 1×

10¹⁶ p-dopant atoms per cubic centimeter.

6. A design structure embodied in a non-transitory computer readable storage medium, which when being executed by a computer implements a method for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a pixel sensor cell comprising;

a photoactive region located within a first semiconductor layer, wherein the first semiconductor layer is located on a second semiconductor layer;

a transistor located partially within the second semiconductor layer, wherein the second semiconductor layer is located on a carrier substrate;

a light blocking layer located interposed between the first semiconductor layer and the second semiconductor layer and shielding the transistor from back side illumination; and

a contact region comprised of a semiconductor material extending through the light blocking layer, wherein the contact region contacts the first semiconductor layer and the second semiconductor layer.