Semiconductor structure and manufacturing method thereof

• US 9,543,373 B2
• Filed: 10/23/2013
• Issued: 01/10/2017
• Est. Priority Date: 10/23/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liang, Shih-Wei, Pan, Hsin-Yu, Wu, Kai-Chiang, Yang, Ching-Feng, Liu, Ming-Kai, Miao, Chia-Chun
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): DINKE, BITEW A
• Application Number:
  US14/061,615
• Publication Number:
  US 20150108635A1
• Time in Patent Office: 1,175 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/0233 Structure of the redistribution layers
• CPC Class Codes: H01L 2224/02373 Layout of the redistribution layers
• CPC Class Codes: H01L 2224/02381 Side view
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/1703 : Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/17181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/17519 : including bump connectors providing primarily thermal dissipation
• CPC Class Codes: H01L 2224/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/2101 : Structure
• CPC Class Codes: H01L 2224/211 : Disposition
• CPC Class Codes: H01L 2224/24105 : Connecting bonding areas at different heights
• CPC Class Codes: H01L 2224/24146 : the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
• CPC Class Codes: H01L 2224/24225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73209 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/80815 : Reflow soldering
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/92124 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3677 : Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/488 : consisting of soldered or bonded constructions bump connectors H01L24/01
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49894 : Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/522 : including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 25/065 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H05K 1/186 : manufactured by mounting on or connecting to patterned circuits before or during embedding
• CPC Class Codes: H05K 2203/0733 : Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
• CPC Class Codes: H05K 3/4682 : Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil

Abstract

A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device.

Claims

1. A semiconductor structure, comprising:

a substrate and a first circuit on the substrate;

a metal structure comprising an active portion and a dummy portion, the active portion electrically coupled with the first circuit through a conductive plug, the dummy portion not being electrically coupled with any circuitry, the active portion and the dummy portion being on a same level of the metal structure;

a semiconductor die bonded to the substrate through a first active bump via a conductive pad on an active surface of the semiconductor die, a passive surface of the semiconductor die contacting the dummy portion of the metal structure, wherein the passive surface is opposite to the active surface;

a dummy bump connected to the dummy portion of the metal structure; and

a molding compound between the substrate and the active surface of the semiconductor die and surrounding the conductive plug;

wherein the dummy bump is surrounded by ambient air.

2. The semiconductor structure of claim 1, wherein the dummy bump is configured to dissipate heat from the passive surface.

3. The semiconductor structure of claim 1, wherein the active portion of the metal structure further comprises a redistribution layer (RDL) connecting to one end of the conductive plug.

4. The semiconductor structure of claim 1, wherein the dummy portion of the metal structure further comprises an under bump metal (UBM) for receiving the dummy bump.

5. The semiconductor structure of claim 1, further comprising a second active bump connected to the active portion of the metal structure.

6. The semiconductor structure of claim 1, wherein the first circuit circuitry includes a post passivation inductor (PPI).

7. The semiconductor structure of claim 6, wherein the PPI is connected to one end of the conductive plug.

8. The semiconductor structure of claim 1, wherein the conductive pad is an under bump metal (UBM), and the conductive pad is connected to an interconnection of the semiconductor die.

9. The semiconductor structure of claim 1, wherein the substrate includes a semiconductor device.

14. The semiconductor structure of claim 1, wherein the metal structure further comprises a redistribution layer (RDL) connecting to the passive surface of the semiconductor die.

15. The semiconductor structure of claim 1, further comprising a dummy bump connected to the dummy portion of the metal structure, wherein the dummy bump comprises a three dimensional surface.

16. The semiconductor structure of Claim 3, wherein the passive surface of the semiconductor die is contacting a bottom of a recess of the RDL.

17. The semiconductor structure of claim 6, wherein the PPI is electrically connected to the active surface of the semiconductor die.

10. A semiconductor structure, comprising:

a three dimensional stack comprising;

a first semiconductor die;

a second semiconductor die electrically connected with the first semiconductor die with a first active bump positioned on a frontside of the second semiconductor die; and

a molding compound between the first semiconductor die and the second semiconductor die;

wherein a dummy portion of a metal structure being over a surface of the three dimensional stack and contacting a backside of the second semiconductor die, the dummy portion neither being electrically coupled to the first semiconductor die nor to the second semiconductor die;

a dummy bump connected with the dummy portion of the metal structure, the dummy bump being surrounded by ambient air; and

an active portion of the metal structure over the surface of the three dimensional stack, not contacting the backside of the second semiconductor die, and configured for electrically connecting the three dimensional stack with an external electronic device, wherein the active portion and the dummy portion are in a same level of the metal structure.

11. The semiconductor structure of claim 10, further comprising a conductive plug between the active portion of the metal structure and the first semiconductor die.

12. The semiconductor structure of claim 10, wherein the dummy bump is configured to connect with a dummy pattern external to the three dimensional stack.

13. The semiconductor structure of claim 10, further comprising a PPI on the first semiconductor die and electrically coupled to the first semiconductor die.

18. The semiconductor structure of claim 12, wherein the dummy pattern is electrically connected to a redistribution layer (RDL).

19. The semiconductor structure of claim 18, wherein a recess portion of the RDL is contacting the backside of the second semiconductor die.

20. The semiconductor structure of claim 10, further comprising a PPI on the first semiconductor die and electrically coupled to the active portion of the metal structure.