Semiconductor switching device including charge storage structure

• US 9,543,398 B2
• Filed: 07/31/2015
• Issued: 01/10/2017
• Est. Priority Date: 08/21/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Laven, Johannes Georg, Mauder, Anton, Dainese, Matteo, Hirler, Franz, Jaeger, Christian, Roesch, Maximilian, Roesner, Wolfgang, Stiftinger, Martin, Strenz, Robert
• Primary Examiner(s): SHOOK, DANIEL P
• Application Number:
  US14/814,758
• Publication Number:
  US 20160056251A1
• Time in Patent Office: 529 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region

Abstract

A semiconductor switching device includes a first load terminal electrically connected to source zones of transistor cells. The source zones form first pn junctions with body zones. A second load terminal is electrically connected to a drain construction that forms second pn junctions with the body zones. Control structures, which include a control electrode and charge storage structures, directly adjoin the body zones. The control electrode controls a load current through the body zones. The charge storage structures insulate the control electrode from the body zones and contain a control charge adapted to induce inversion channels in the body zones in the absence of a potential difference between the control electrode and the first load electrode.

Claims

1. A semiconductor device, comprising:

a first load terminal electrically connected to source zones of transistor cells, wherein the source zones form first pn junctions with body zones;

a second load terminal electrically connected to a drain construction forming second pn junctions with the body zones; and

control structures directly adjoining the body zones, the control structures comprising a control electrode and charge storage structures, the control electrode configured to control a load current through the body zones, the charge storage structures insulating the control electrode from the body zones and containing a control charge adapted to induce inversion channels in the body zones in the absence of a potential difference between the control electrode and the first load terminal,

wherein the body zones are formed in semiconductor mesas formed from portions of a semiconductor body and separated from each other by the control structures.

2. The semiconductor device of claim 1, wherein the charge storage structures are sandwiched between the control electrode and at least the body zones.

3. The semiconductor device of claim 1, wherein the charge storage structures are charged portions of a control dielectric that separates the control electrode from a semiconductor body including the body zones.

4. The semiconductor device of claim 1, wherein the charge storage structures comprise charge storage layers, first dielectrics sandwiched between the body zones and the charge storage layers, and second dielectrics sandwiched between the charge storage layers and the control electrode.

5. The semiconductor device of claim 4, wherein the charge storage layers comprise a conductive material.

6. The semiconductor device of claim 5, further comprising:

a wiring structure connecting the charge storage layers with a programming pad.

7. The semiconductor device of claim 4, wherein the charge storage layers comprise dielectric charge trapping layers.

8. The semiconductor device of claim 4, wherein the first dielectric is thicker than the second dielectric.

9. The semiconductor device of claim 4, further comprising:

program electrodes sandwiched between the control electrode and the charge storage layers.

10. The semiconductor switching device of claim 1, wherein the charged layer is a dielectric structure embedding semiconducting nanocrystallites.

11. A semiconductor switching device, comprising:

transistor cells comprising source zones forming first pn junctions with body zones, the body zones forming second pn junctions with a drain construction;

auxiliary cells comprising charge carrier transfer zones forming third pn junctions with desaturation portions of the drain construction;

a first control structure comprising a first portion of a control electrode and configured to induce an inversion channel through the body zones in an on state;

a second control structure directly adjoining the desaturation portions, the second control structure comprising a second portion of the control electrode and a charged layer sandwiched between the second portion of the control electrode and the desaturation portions and containing a control charge adapted to induce an inversion layer in the desaturation portions in the on state.

12. The semiconductor switching device of claim 11, wherein the control charge is adapted to induce the inversion layer in the desaturation portions at a first gate voltage applied between the control electrode and the source zones in the on state and to induce no inversion layer in the desaturation portions at a second gate voltage applied between the control electrode and the source zones in the on state.

13. The semiconductor switching device of claim 11, further comprising:

a first load terminal electrically connected to the source zones, the body zones and the charge carrier transfer zones, and

a second load terminal electrically connected to the drain construction.

14. The semiconductor switching device of claim 11, wherein the source zones, the body zones and the charge carrier transfer zones are formed in semiconductor mesas formed from portions of a semiconductor body, and the control structures separate neighboring ones of the semiconductor mesas.

15. The semiconductor switching device of claim 11, further comprising:

a first dielectric sandwiched between the semiconductor body and the charged layer, and a second dielectric sandwiched between the charged layer and the control electrode.

16. The semiconductor switching device of claim 11, wherein the charged layer is a conductive layer.

17. The semiconductor switching device of claim 16, further comprising:

a wiring structure connecting the charged layer with a programming pad.

18. The semiconductor switching device of claim 11, wherein the charged layer is a dielectric charge trapping layer.

19. The semiconductor switching device of claim 11, wherein the first dielectrics are thicker than the second dielectrics.

20. The semiconductor switching device of claim 11, wherein the drain construction includes barrier zones and a drift zone, a mean net dopant concentration of the barrier zones exceeds at least five times a mean net dopant concentration in the drift zone and the charge storage structure is sandwiched between the control electrode and at least some of the barrier zones.

21. The semiconductor switching device of claim 11, wherein the charged layer is a dielectric structure embedding semiconducting nanocrystallites.

22. The semiconductor switching device of claim 11, wherein the auxiliary cells are devoid of doped zones that are both electrically connected to the first load terminal and form pn junctions with the charge carrier transfer zones.