Integrated circuit

• US 9,544,008 B2
• Filed: 04/27/2016
• Issued: 01/10/2017
• Est. Priority Date: 08/05/2005
• Status: Active Grant

• Current Assignee: Panasonic Holdings Corporation
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Miyoshi, Kenichi, Suzuki, Hidetoshi, Hiramatsu, Katsuhiko, Wengerter, Christian, Golitschek Edler Von Elbwart, Alexander
• Primary Examiner(s): Timory, Kabir A
• Application Number:
  US15/139,880
• Publication Number:
  US 20160241296A1
• Time in Patent Office: 258 Days
• US Class Current: 1/1
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04B 15/00 Suppression or limitation of noise or interference by means associated with receiver H04B1/10
• CPC Class Codes: H04L 1/0042 Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape H04L1/0067 takes precedence
• CPC Class Codes: H04L 25/0202 Channel estimation
• CPC Class Codes: H04L 25/0212 of impulse response
• CPC Class Codes: H04L 25/0224 using sounding signals
• CPC Class Codes: H04L 27/04 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/18 Phase-modulated carrier systems, i.e. using phase-shift keying H04L27/32 takes precedence
• CPC Class Codes: H04L 27/183 Multiresolution systems
• CPC Class Codes: H04L 27/34 Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
• CPC Class Codes: H04L 27/36 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/38 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 5/0046 Determination of how many bits are transmitted on different sub-channels

Abstract

Wireless communication wherein channel estimation accuracy is improved while keeping the position of each bit in a frame, even when a modulation system having a large modulation multiple value is used for a data symbol. An encoding operation encodes and outputs transmitting data (bit string) and a bit converting operation converts at least one bit of a plurality of bits constituting a data symbol to be used for channel estimation, among the encoded bit strings, into ‘1’ or ‘0’. A modulating operation modulates the bit string inputted from the bit converting operation by using a single modulation mapper and a plurality of data symbols are generated.

Claims

1. An integrated circuit comprising:

transmitting circuitry, which, in operation, controls transmission of control information indicating a number of bits; and

receiving circuitry, which, in operation, controls reception of a bit sequence, in which each of the number of bits indicated by the control information of a plurality of bits is forcibly set to a 1 and which is modulated by mapping the plurality of bits on a single modulation mapper, wherein the plurality of bits forms a modulation symbol in the bit sequence, and the single modulation mapper has first signal points,

wherein each of the number of bits is forcibly set to the 1 in a way that the plurality of bits are mapped to one of second signal points, which are a part of the first signal points, a distance between the second signal points being equivalent to a largest of distances existing among the first signal points in an I-Q plane of the single modulation mapper.

2. The integrated circuit according to claim 1, wherein the single modulation mapper has 16 first signal points for 16 QAM, and the second signal points are a constellation of BPSK, QPSK or 8-PSK which is included in the single modulation mapper.

3. The integrated circuit according to claim 1, wherein the control information indicates two as the number of bits, and the bit sequence is generated by forcibly setting each of the lowest two bits of the plurality of bits to the 1.

4. The integrated circuit according to claim 1, wherein the control information indicates three as the number of bits, and the bit sequence is generated by forcibly setting each of the lowest three bits of the plurality of bits to the 1.

5. The integrated circuit according to claim 1, wherein the control information indicates four as the number of bits, and the bit sequence is generated by forcibly setting each of the lowest four bits of the plurality of bits to the 1.

6. An integrated circuit comprising:

transmitting circuitry, which, in operation, controls transmission of control information indicating a number of bits; and

receiving circuitry, which, in operation, controls reception of a bit sequence, in which each of the number of bits indicated by the control information of a plurality of bits is forcibly set to a 1 and which is modulated by mapping the plurality of bits on a single modulation mapper, wherein the plurality of bits forms a modulation symbol in the bit sequence, and the single modulation mapper has first signal points,

wherein each of the number of bits is forcibly set to the 1 in a way that the plurality of bits are mapped to one of second signal points, which are a part of the first signal points, such that said modulation symbol is detected by positive or negative decision only with respect to at least one of an I-axis and a Q-axis in the single modulation mapper.

7. The integrated circuit according to claim 6, wherein the single modulation mapper has 16 first signal points for 16 QAM, and the second signal points are a constellation of BPSK, QPSK or 8-PSK which is included in the single modulation mapper.

8. The integrated circuit according to claim 6, wherein the control information indicates two as the number of bits, and the bit sequence is generated by forcibly setting each of the lowest two bits of the plurality of bits to the 1.

9. The integrated circuit according to claim 6, wherein the control information indicates three as the number of bits, and the bit sequence is generated by forcibly setting each of the lowest three bits of the plurality of bits to the 1.

10. The integrated circuit according to claim 6, wherein the control information indicates four as the number of bits, and the bit sequence is generated by forcibly setting each of the lowest four bits of the plurality of bits to the 1.

11. An integrated circuit comprising:

at least one output; and

circuitry coupled to the at least one output, wherein the circuitry, in operation;

controls transmission of control information indicating a number of bits; and

controls reception of a bit sequence, in which each of the number of bits indicated by the control information of a plurality of bits is forcibly set to a 1 and which is modulated by mapping the plurality of bits on a single modulation mapper, wherein the plurality of bits forms a modulation symbol in the bit sequence, and the single modulation mapper has first signal points,

wherein each of the number of bits is forcibly set to the 1 in a way that the plurality of bits are mapped to one of second signal points, which are a part of the first signal points, a distance between the second signal points being equivalent to a largest of distances existing among the first signal points in an I-Q plane of the single modulation mapper.

12. The integrated circuit according to claim 11, wherein the single modulation mapper has 16 first signal points for 16 QAM, and the second signal points are a constellation of BPSK, QPSK or 8-PSK which is included in the single modulation mapper.

13. The integrated circuit according to claim 11, wherein the control information indicates two as the number of bits, and the bit sequence is generated by forcibly setting each of the lowest two bits of the plurality of bits to the 1.

14. The integrated circuit according to claim 11, wherein the control information indicates three as the number of bits, and the bit sequence is generated by forcibly setting each of the lowest three bits of the plurality of bits to the 1.

15. The integrated circuit according to claim 11, wherein the control information indicates four as the number of bits, and the bit sequence is generated by forcibly setting each of the lowest four bits of the plurality of bits to the 1.

16. An integrated circuit comprising:

at least one output; and

circuitry coupled to the at least one output, wherein the circuitry, in operation;

controls transmission of control information indicating a number of bits; and

controls reception of a bit sequence, in which each of the number of bits indicated by the control information of a plurality of bits is forcibly set to a 1 and which is modulated by mapping the plurality of bits on a single modulation mapper, wherein the plurality of bits forms a modulation symbol in the bit sequence, and the single modulation mapper has first signal points,

wherein each of the number of bits is forcibly set to the 1 in a way that the plurality of bits are mapped to one of second signal points, which are a part of the first signal points, such that said modulation symbol is detected by positive or negative decision only with respect to at least one of an I-axis and a Q-axis in the single modulation mapper.

17. The integrated circuit according to claim 16, wherein the single modulation mapper has 16 first signal points for 16 QAM, and the second signal points are a constellation of BPSK, QPSK or 8-PSK which is included in the single modulation mapper.

18. The integrated circuit according to claim 16, wherein the control information indicates two as the number of bits, and the bit sequence is generated by forcibly setting each of the lowest two bits of the plurality of bits to the 1.

19. The integrated circuit according to claim 16, wherein the control information indicates three as the number of bits, and the bit sequence is generated by forcibly setting each of the lowest three bits of the plurality of bits to the 1.

20. The integrated circuit according to claim 16, wherein the control information indicates four as the number of bits, and the bit sequence is generated by forcibly setting each of the lowest four bits of the plurality of bits to the 1.