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Multiphase receiver with equalization circuitry

  • US 9,544,169 B2
  • Filed: 01/17/2014
  • Issued: 01/10/2017
  • Est. Priority Date: 10/19/1999
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit, comprising:

  • a first circuit to produce a first decision regarding a first logic state of a first data symbol associated with a first portion of a clock cycle;

    a second circuit to produce a second decision regarding a second logic state of a second data symbol associated with a second portion of the clock cycle; and

    an equalizing circuit, having an input coupled to an output of the first circuit and an output coupled to an output of the second circuit, to compensate for intersymbol interference affecting the second circuit dependent on an output of the first circuit.

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