Multiphase receiver with equalization circuitry

• US 9,544,169 B2
• Filed: 01/17/2014
• Issued: 01/10/2017
• Est. Priority Date: 10/19/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared L., Garlepp, Bruno W., Chau, Pak S., Donnelly, Kevin S., Horowitz, Mark A., Sidiropoulos, Stefanos, Garrett, Billy W. Jr., Werner, Carl W.
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US14/158,675
• Publication Number:
  US 20140286389A1
• Time in Patent Office: 1,089 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/0296 Arrangements to ensure DC-balance
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03057 : with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/08 : Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/4902 : Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 25/4917 : using multilevel codes
• CPC Class Codes: H04L 7/0331 : with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/0332 : with an integrator-detector

Abstract

An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the sense amplifier by applying to the input of the sense amplifier a portion of a previous signal representing a previous bit. The integrated circuit device further includes a latch, coupled to the sense amplifier, to output the logic level.

Claims

1. An integrated circuit, comprising:

a first circuit to produce a first decision regarding a first logic state of a first data symbol associated with a first portion of a clock cycle;

a second circuit to produce a second decision regarding a second logic state of a second data symbol associated with a second portion of the clock cycle; and

an equalizing circuit, having an input coupled to an output of the first circuit and an output coupled to an output of the second circuit, to compensate for intersymbol interference affecting the second circuit dependent on an output of the first circuit.

2. The integrated circuit of claim 1, where the equalizing circuit is further to compensate for intersymbol interference affecting the first circuit dependent on an output of the second circuit.

3. The integrated circuit of claim 2, where the equalizing circuit further comprises a first adjustment circuit to adjust a voltage used by the equalizing circuit to compensate for intersymbol interference affecting the second circuit dependent on the output of the first circuit, and a second adjustment circuit to adjust a voltage used by the equalizing circuit to compensate for intersymbol interference affecting the first circuit dependent on the output of the second circuit.

4. The integrated circuit of claim 2, where the integrated circuit further comprises a preamplifier circuit, the integrated circuit to cause each of the first and second circuits to sample an electrical input signal on reciprocal edges of a clock signal.

5. The integrated circuit of claim 4, where:

the preamplifier circuit is to provide a differential output signal to each of the first and second circuits dependent on the electrical input signal; and

the equalizing circuit is to compensate for the intersymbol interference by adjusting a first one of two components of the differential output signal dependent on an immediately prior data symbol carried by the differential output signal, and by adjusting the second one of two components of the differential output signal dependent on the immediately prior data symbol carried by the differential output signal.

6. The integrated circuit of claim 5, where the equalizing circuit is to compensate for the intersymbol interference by adjusting the first one of two components of the differential output signal dependent on voltage carried by the second one of the two components for the immediately prior data symbol carried by the differential output signal, and by adjusting the second one of two components of the differential output signal dependent on voltage carried by the first one of the two components for the immediately prior data symbol carried by the differential output signal.

9. The integrated circuit of claim 1, further comprising a circuit to adjust a voltage used by the equalizing circuit to compensate for intersymbol interference affecting the second circuit dependent on the output of the first circuit and a voltage used by the equalizing circuit to compensate for intersymbol interference affecting the first circuit dependent on the output of the second circuit.

10. The integrated circuit of claim 9, where the equalizing circuit further comprises a register to receive and store a value representing the voltage used by the equalizing circuit to compensate for intersymbol interference affecting at least one of the first circuit and the second circuit, and a digital-to-analog converter to receive the value from the register and to responsively generate an analog voltage.

11. The integrated circuit of claim 10, where the electrical input signal is a differential input signal received by the integrated circuit, and where the equalizing circuit is to compensate for the intersymbol interference by adjusting voltage provided by each component of the differential signal dependent on relative voltage of the other component associated with an immediately prior data symbol carried by the differential input signal.

12. The integrated circuit of claim 1, wherein the equalizing circuit comprises a first adjustment circuit to adjust a voltage used by the equalizing circuit to compensate for intersymbol interference affecting the second circuit dependent on the output of the first circuit.

7. An integrated circuit, comprising:

a first circuit, including a first integrating receiver, to produce a first decision regarding a first logic state of a first data symbol associated with a first portion of a clock cycle;

a second circuit, including a second integrating receiver, to produce a second decision regarding a second logic state of a second data symbol associated with a second portion of the clock cycle; and

an equalizing circuit, having an input coupled to an output of the first integrating receiver of the first circuit and an output coupled to an output of the second integrating receiver of the second circuit, to compensate for intersymbol interference affecting the second circuit dependent on an output of the first circuit.

8. The integrated circuit of claim 7, where:

each of the first and second circuits further comprises a sense amplifier and a latch, where each sense amplifier is to receive a present signal representing a present data symbol and to produce a decision regarding the present data symbol and where the corresponding latch is to output a logic level dependent on the respective decision; and

the equalization circuit is to precharge each sense amplifier in dependence on the immediately prior data symbol carried by the electrical input signal.

13. An integrated circuit, comprising:

a first circuit, including a first receiver, to produce a first decision regarding a first logic state of a first data symbol associated with a first portion of a clock cycle;

a second circuit, including a second receiver, to produce a second decision regarding a second logic state of a second data symbol associated with a second portion of the clock cycle; and

an equalizing circuit, having an input coupled to an output of the first receiver of the first circuit and an output coupled to an output of the second receiver of the second circuit, to compensate for intersymbol interference affecting the second data symbol dependent on an output of the first circuit.

14. The integrated circuit of claim 13, where the equalizing circuit is further to compensate for intersymbol interference affecting the first data symbol dependent on an output of the second circuit.

15. The integrated circuit of claim 14, where the equalizing circuit further comprises a first adjustment circuit to adjust a voltage used by the equalizing circuit to compensate for intersymbol interference affecting the second data symbol dependent on the output of the first circuit and a second adjustment circuit to adjust a voltage used by the equalizing circuit to compensate for intersymbol interference affecting the first data symbol dependent on the output of the second circuit.

16. The integrated circuit of claim 13, where the first receiver and the second receiver each comprises an integrating receiver.

17. An integrated circuit comprising:

first and second receiver circuits to receive interleaved even and odd portions of a serial data stream, and

an equalizing circuit, having an input coupled to an output of the first receiver circuit and an output coupled to an output of the second receiver circuit, to compensate for intersymbol interference affecting the second receiver circuit dependent on an output of the first receiver circuit.

18. The integrated circuit of claim 17, where the equalizing circuit is further to compensate for intersymbol interference affecting the first receiver circuit dependent on an output of the second receiver circuit.

19. The integrated circuit of claim 17, where the equalizing circuit further comprises a first adjustment circuit to adjust a voltage used by the equalizing circuit to compensate for intersymbol interference affecting an output of the second receiver circuit, and a second adjustment circuit to adjust a voltage used by the equalizing circuit to compensate for intersymbol interference affecting an output of the first receiver circuit.

20. The integrated circuit of claim 17, where the interleaved portions of the serial data stream are received by the first and second receiver circuits to produce a stream of data symbols, and the equalizing circuit is to compensate for intersymbol interference by adjusting a first data symbol based on a second data symbol received before the first data symbol.