Method for testing data packet signal transceivers using interleaved device setup and testing

• US 9,544,787 B2
• Filed: 09/03/2013
• Issued: 01/10/2017
• Est. Priority Date: 09/03/2013
• Status: Active Grant

• Current Assignee: LitePoint Corporation (Teradyne Incorporated)
• Original Assignee: LitePoint Corporation (Teradyne Incorporated)
• Inventors: Zhao, He, Olgaard, Christian Volf
• Primary Examiner(s): SEFCHECK, GREGORY B
• Application Number:
  US14/017,041
• Publication Number:
  US 20150063133A1
• Time in Patent Office: 1,225 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H04B 17/0085 using test signal generators
• CPC Class Codes: H04B 17/21 for calibration; for correcting measurements
• CPC Class Codes: H04W 24/08 Testing, supervising or monitoring using real traffic

Abstract

A method of using tester data packet signals and control instructions for testing multiple data packet signal transceiver devices under test (DUTs). During mutually alternating time intervals, selected ones of which are substantially contemporaneous, multiple tester data packet signals and DUT control instructions are used for concurrent testing of multiple DUTs.

Claims

1. A method of using tester data packet signals and control instructions for testing multiple data packet signal transceiver devices under test (DUTs), comprising:

receiving, with each one of first one or more of a plurality of DUTs with data packet signal reception enabled during one of a first plurality of tester signal intervals, a respective one of a plurality of tester data packet signals;

receiving, with each one of second one or more of said plurality of DUTs with data packet signal reception enabled during one of a second plurality of tester signal intervals, a respective one of said plurality of tester data packet signals;

executing, with each one of said first one or more of said plurality of DUTs with data packet signal reception disabled during one of a first plurality of instruction intervals, a plurality of DUT control instructions to configure each one of said first one or more of said plurality of DUTs to receive a respective one of said plurality of tester data packet signals with one or more of an upcoming prescribed power level, data rate or modulation type; and

executing, with each one of said second one or more of said plurality of DUTs with data packet signal reception disabled during one of a second plurality of instruction intervals, a plurality of DUT control instructions to configure each one of said second one or more of said plurality of DUTs to receive a respective one of said plurality of tester data packet signals with one or more of an upcoming prescribed power level, data rate or modulation type;

wherein

respective ones of said first plurality of tester signal intervals and said first plurality of instruction intervals are mutually alternating,

respective ones of said second plurality of tester signal intervals and said second plurality of instruction intervals are mutually alternating,

respective ones of said first plurality of tester signal intervals are substantially contemporaneous with respective ones of said second plurality of instruction intervals, and

respective ones of said second plurality of tester signal intervals are substantially contemporaneous with respective ones of said first plurality of instruction intervals.

2. The method of claim 1, wherein:

respective ones of said first and second pluralities of tester signal intervals are mutually alternating; and

respective ones of said first and second pluralities of instruction intervals are mutually alternating.

3. The method of claim 1, wherein said respective ones of said first and second pluralities of tester signal intervals are mutually exclusive.

4. The method of claim 1, wherein said respective ones of said first and second pluralities of instruction intervals are mutually exclusive.

5. The method of claim 1, wherein said respective ones of said first and second pluralities of instruction intervals are partially contemporaneous.

6. The method of claim 1, wherein:

respective ones of said first and second pluralities of tester signal intervals comprise odd and even ones, respectively, of a sequence of tester signal intervals;

respective ones of said first and second pluralities of instruction intervals comprise odd and even ones, respectively, of a sequence of instruction intervals;

respective odd ones of said sequence of tester signal intervals are substantially contemporaneous with respective even ones of said sequence of instruction intervals; and

respective even ones of said sequence of tester signal intervals are substantially contemporaneous with respective odd ones of said sequence of instruction intervals.

7. A method of providing tester data packet signals and control instructions for testing multiple data packet signal transceiver devices under test (DUTs), comprising:

providing, for each one of first one or more of a plurality of DUTs with data packet signal reception enabled during one of a first plurality of tester signal intervals, a respective one of a plurality of tester data packet signals;

providing, for each one of second one or more of said plurality of DUTs with data packet signal reception enabled during one of a second plurality of tester signal intervals, a respective one of said plurality of tester data packet signals;

providing, for execution by each one of said first one or more of said plurality of DUTs with data packet signal reception disabled during one of a first plurality of instruction intervals, a plurality of DUT control instructions to configure each one of said first one or more of said plurality of DUTs to receive a respective one of said plurality of tester data packet signals with one or more of an upcoming prescribed power level, data rate or modulation type; and

providing, for execution by each one of said second one or more of said plurality of DUTs with data packet signal reception disabled during one of a second plurality of instruction intervals, a plurality of DUT control instructions to configure each one of said second one or more of said plurality of DUTs to receive a respective one of said plurality of tester data packet signals with one or more of an upcoming prescribed power level, data rate or modulation type;

wherein

respective ones of said first plurality of tester signal intervals and said first plurality of instruction intervals are mutually alternating,

respective ones of said second plurality of tester signal intervals and said second plurality of instruction intervals are mutually alternating,

respective ones of said first plurality of tester signal intervals are substantially contemporaneous with respective ones of said second plurality of instruction intervals, and

respective ones of said second plurality of tester signal intervals are substantially contemporaneous with respective ones of said first plurality of instruction intervals.

8. The method of claim 7, wherein:

respective ones of said first and second pluralities of tester signal intervals are mutually alternating; and

respective ones of said first and second pluralities of instruction intervals are mutually alternating.

9. The method of claim 7, wherein said respective ones of said first and second pluralities of tester signal intervals are mutually exclusive.

10. The method of claim 7, wherein said respective ones of said first and second pluralities of instruction intervals are mutually exclusive.

11. The method of claim 7, wherein said respective ones of said first and second pluralities of instruction intervals are partially contemporaneous.

12. The method of claim 7, wherein:

respective ones of said first and second pluralities of tester signal intervals comprise odd and even ones, respectively, of a sequence of tester signal intervals;

respective ones of said first and second pluralities of instruction intervals comprise odd and even ones, respectively, of a sequence of instruction intervals;

respective odd ones of said sequence of tester signal intervals are substantially contemporaneous with respective even ones of said sequence of instruction intervals; and

respective even ones of said sequence of tester signal intervals are substantially contemporaneous with respective odd ones of said sequence of instruction intervals.