Methods and apparatuses for memory power reduction

• US 9,547,361 B2
• Filed: 04/29/2015
• Issued: 01/17/2017
• Est. Priority Date: 04/29/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Taha, Ali, Chun, Dexter Tamio
• Primary Examiner(s): Stoynov, Stefan
• Application Number:
  US14/700,017
• Publication Number:
  US 20160320826A1
• Time in Patent Office: 629 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory
• CPC Class Codes: G06F 2212/217 Hybrid disk, e.g. using both magnetic and solid state storage devices
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 14/0009 in which the volatile element is a DRAM cell
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatuses for memory power reduction are provided. The apparatus determines whether to store data into a DRAM or an NVRAM during an idle state of a processor based on power consumption by the DRAM in association with refreshing the data in the DRAM and use of the data stored in the DRAM by the processor, based on power consumption by the NVRAM in association with use of the data stored in the NVRAM by the processor, and based on a duty cycle associated with current drawn in a first power state and a second power state in association with the data. The NVRAM is a type of non-volatile random-access memory other than flash memory. The processor stores the data into one of the DRAM or the NVRAM based on the determination whether to store the data in the DRAM or the NVRAM.

Claims

1. A method of memory power reduction by an apparatus, comprising:

determining whether to store data into a dynamic random-access memory (DRAM) or a non-volatile random-access memory (NVRAM) based on a power consumption by the DRAM in association with refreshing the data in the DRAM and use of the data stored in the DRAM by a processor, based on a power consumption by the NVRAM in association with use of the data stored in the NVRAM by the processor, and based on a duty cycle associated with current drawn in a first power state and a second power state in association with the data, said NVRAM being a type of random-access memory other than flash memory; and

storing the data into one of the DRAM or the NVRAM based on the determination whether to store the data in the DRAM or the NVRAM.

2. The method of claim 1, wherein the determination whether to store the data in the DRAM or the NVRAM comprises:

determining, based on said duty cycle, whether the DRAM consumes more power or the NVRAM consumes more power in association with the data; and

determining to store the data into the DRAM when the NVRAM consumes more power than the DRAM in association with the data, and to store the data into the NVRAM when the NVRAM consumes less power than the DRAM in association with the data.

3. The method of claim 2, wherein the determination whether the DRAM or the NVRAM consumes more power in association with the data is further based on at least one of a determined average current drawn by the DRAM in association with the data or a determined average current drawn by the NVRAM in association with the data.

4. The method of claim 2, wherein the determination whether the DRAM or the NVRAM consumes more power in association with the data is further based on at least one of a determined first-power-state current drawn by the DRAM during the first power state of the processor in association with the data, a determined second-power-state current drawn by the DRAM during the second power state of the processor in association with the data, said duty cycle associated with current drawn in the first power state and the second power state by the DRAM in association with the data, a determined first-power-state current drawn by the NVRAM during the first power state of the processor in association with the data, a determined second-power-state current drawn by the NVRAM during the second power state of the processor in association with the data, and said duty cycle associated with current drawn in the first power state and the second power state by the NVRAM in association with the data.

5. The method of claim 1, wherein the determination whether to store the data in the DRAM or the NVRAM comprises:

determining a use case for the data; and

accessing a table associated with use cases to determine whether to store the data in the NVRAM or the DRAM based on the determined use case.

6. The method of claim 5, further comprising:

determining that a use case is not included in the table;

determining whether the use case consumes more or less power in the DRAM or the NVRAM; and

listing the use case in the table with information indicating whether the DRAM or the NVRAM should be used in association with the use case.

7. The method of claim 5, wherein the determination whether to store the data in the DRAM or the NVRAM occurs upon an initial booting of the processor.

8. The method of claim 1, wherein the determination whether to store the data in the DRAM or the NVRAM comprises:

storing the data into the DRAM;

determining a DRAM power consumption in the DRAM in association with the data;

determining that the processor has been in an idle-standby state with respect to the data for longer than a threshold time period;

moving the data from the DRAM to the NVRAM;

determining an NVRAM power consumption in the NVRAM in association with the data;

determining to keep the data stored in the NVRAM when the NVRAM power consumption is less than the DRAM power consumption; and

determining to move the data back to the DRAM when the NVRAM power consumption is greater than the DRAM power consumption.

9. The method of claim 1, wherein the determination whether to store the data in the DRAM or the NVRAM comprises:

determining whether the processor is in an idle-standby state; and

determining to store the data in the NVRAM when the processor is in the idle-standby state and to store the data in the DRAM when the processor is not in the idle-standby state.

10. The method of claim 1, wherein the determination whether to store the data in the DRAM or the NVRAM comprises:

determining whether the processor is processing data in association with a plurality of subscriber identity module (SIM) cards; and

determining to store the data in the DRAM when the processor is determined to be processing data in association with a plurality of SIM cards.

11. The method of claim 1, wherein the data is loaded into the DRAM or the NVRAM from flash memory resident on a system on a chip (SoC) integrated circuit (IC), the SoC IC including the processor and the flash memory.

12. The method of claim 1, wherein the NVRAM comprises at least one of magnetoresistive random-access memory (MRAM), phase-change random-access memory (PRAM), resistive random-access memory (RRAM), ferroelectric random-access memory (FeRAM), or nano-random-access memory (NRAM).

13. The method of claim 1, wherein the first power state is a high power state and the second power state is a low power state.

14. The method of claim 1, further comprising accessing the stored data periodically from one of the DRAM or the NVRAM during the first power state associated with the duty cycle.

15. An apparatus for memory power reduction, comprising:

means for determining whether to store data into a dynamic random-access memory (DRAM) or a non-volatile random-access memory (NVRAM) based on a power consumption by the DRAM in association with refreshing the data in the DRAM and use of the data stored in the DRAM by a processor, based on a power consumption by the NVRAM in association with use of the data stored in the NVRAM by the processor, and based on a duty cycle associated with current drawn in a first power state and a second power state in association with the data, said NVRAM being a type of random-access memory other than flash memory; and

means for storing the data into one of the DRAM or the NVRAM based on the determination whether to store the data in the DRAM or the NVRAM.

16. The apparatus of claim 15, wherein to determine whether to store the data in the DRAM or the NVRAM, the means for determining is configured to:

determine, based on said duty cycle, whether the DRAM consumes more power or the NVRAM consumes more power in association with the data; and

determine to store the data into the DRAM when the NVRAM consumes more power than the DRAM in association with the data, and to store the data into the NVRAM when the NVRAM consumes less power than the DRAM in association with the data.

17. The apparatus of claim 16, wherein the determination whether the DRAM or the NVRAM consumes more power in association with the data is further based on at least one of a determined average current drawn by the DRAM in association with the data or a determined average current drawn by the NVRAM in association with the data.

18. The apparatus of claim 16, wherein the determination whether the DRAM or the NVRAM consumes more power in association with the data is further based on at least one of a determined first-power-state current drawn by the DRAM during the first power state of the processor in association with the data, a determined second-power-state current drawn by the DRAM during the second power state of the processor in association with the data, said duty cycle associated with current drawn in the first power state and the second power state by the DRAM in association with the data, a determined first-power-state current drawn by the NVRAM during the first power state of the processor in association with the data, a determined second-power-state current drawn by the NVRAM during the second power state of the processor in association with the data, and said duty cycle associated with current drawn in the first power state and the second power state by the NVRAM in association with the data.

19. The apparatus of claim 15, wherein to determine whether to store the data in the DRAM or the NVRAM, the means for determining is configured to:

determine a use case for the data; and

access a table associated with use cases to determine whether to store the data in the NVRAM or the DRAM based on the determined use case.

20. The apparatus of claim 19, further comprising:

means for determining that a use case is not included in the table;

means for determining whether the use case consumes more or less power in the DRAM or the NVRAM; and

means for listing the use case in the table with information indicating whether the DRAM or the NVRAM should be used in association with the use case.

21. The apparatus of claim 19, wherein the determination whether to store the data in the DRAM or the NVRAM occurs upon an initial booting of the processor.

22. The apparatus of claim 15, wherein to determine whether to store the data in the DRAM or the NVRAM, the means for determining is configured to:

store the data into the DRAM;

determine a DRAM power consumption in the DRAM in association with the data;

determine that the processor has been in an idle-standby state with respect to the data for longer than a threshold time period;

move the data from the DRAM to the NVRAM;

determine an NVRAM power consumption in the NVRAM in association with the data;

determine to keep the data stored in the NVRAM when the NVRAM power consumption is less than the DRAM power consumption; and

determine to move the data back to the DRAM when the NVRAM power consumption is greater than the DRAM power consumption.

23. The apparatus of claim 15, wherein to determine whether to store the data in the DRAM or the NVRAM, the means for determining is configured to:

determine whether the processor is in an idle-standby state; and

determine to store the data in the NVRAM when the processor is in the idle-standby state and to store the data in the DRAM when the processor is not in the idle-standby state.

24. The apparatus of claim 15, wherein to determine whether to store the data in the DRAM or the NVRAM, the means for determining is configured to:

determine whether the processor is processing data in association with a plurality of subscriber identity module (SIM) cards; and

determine to store the data in the DRAM when the processor is determined to be processing data in association with a plurality of SIM cards.

25. The apparatus of claim 15, wherein the data is loaded into the DRAM or the NVRAM from flash memory resident on a system on a chip (SoC) integrated circuit (IC), the SoC IC including the processor and the flash memory.

26. The apparatus of claim 15, wherein the NVRAM comprises at least one of magnetoresistive random-access memory (MRAM), phase-change random-access memory (PRAM), resistive random-access memory (RRAM), ferroelectric random-access memory (FeRAM), or nano-random-access memory (NRAM).

27. The apparatus of claim 15, wherein the first power state is a high power state and the second power state is a low power state.

28. The apparatus of claim 15, further comprising means for accessing the stored data periodically from one of the DRAM or the NVRAM during the first power state associated with the duty cycle.

29. An apparatus for memory power reduction, comprising:

a memory; and

at least one processor coupled to the memory and configured to;

determine whether to store data into a dynamic random-access memory (DRAM) or a non-volatile random-access memory (NVRAM) based on a power consumption by the DRAM in association with refreshing the data in the DRAM and use of the data stored in the DRAM by a processor, based on a power consumption by the NVRAM in association with use of the data stored in the NVRAM by the processor, and based on a duty cycle associated with current drawn in a first power state and a second power state in association with the data, said NVRAM being a type of random-access memory other than flash memory; and

store the data into one of the DRAM or the NVRAM based on the determination whether to store the data in the DRAM or the NVRAM.

30. The apparatus of claim 29, wherein to determine whether to store the data in the DRAM or the NVRAM, the at least one processor is configured to:

determine, based on said duty cycle, whether the DRAM consumes more power or the NVRAM consumes more power in association with the data; and

determine to store the data into the DRAM when the NVRAM consumes more power than the DRAM in association with the data, and to store the data into the NVRAM when the NVRAM consumes less power than the DRAM in association with the data.

31. The apparatus of claim 30, wherein the determination whether the DRAM or the NVRAM consumes more power in association with the data is further based on at least one of a determined average current drawn by the DRAM in association with the data or a determined average current drawn by the NVRAM in association with the data.

32. The apparatus of claim 30, wherein the determination whether the DRAM or the NVRAM consumes more power in association with the data is further based on at least one of a determined first-power-state current drawn by the DRAM during the first power state of the processor in association with the data, a determined second-power-state current drawn by the DRAM during the second power state of the processor in association with the data, said duty cycle associated with current drawn in the first power state and the second power state by the DRAM in association with the data, a determined first-power-state current drawn by the NVRAM during the first power state of the processor in association with the data, a determined second-power-state current drawn by the NVRAM during the second power state of the processor in association with the data, and said duty cycle associated with current drawn in the first power state and the second power state by the NVRAM in association with the data.

33. The apparatus of claim 29, wherein to determine whether to store the data in the DRAM or the NVRAM, the at least one processor is configured to:

determine a use case for the data; and

access a table associated with use cases to determine whether to store the data in the NVRAM or the DRAM based on the determined use case.

34. The apparatus of claim 33, wherein the at least one processor is further configured to:

determine that a use case is not included in the table;

determine whether the use case consumes more or less power in the DRAM or the NVRAM; and

list the use case in the table with information indicating whether the DRAM or the NVRAM should be used in association with the use case.

35. The apparatus of claim 33, wherein the determination whether to store the data in the DRAM or the NVRAM occurs upon an initial booting of the processor.

36. The apparatus of claim 29, wherein to determine whether to store the data in the DRAM or the NVRAM, the at least one processor is configured to:

store the data into the DRAM;

determine a DRAM power consumption in the DRAM in association with the data;

determine that the processor has been in an idle-standby state with respect to the data for longer than a threshold time period;

move the data from the DRAM to the NVRAM;

determine an NVRAM power consumption in the NVRAM in association with the data;

determine to keep the data stored in the NVRAM when the NVRAM power consumption is less than the DRAM power consumption; and

determine to move the data back to the DRAM when the NVRAM power consumption is greater than the DRAM power consumption.

37. The apparatus of claim 29, wherein to determine whether to store the data in the DRAM or the NVRAM, the at least one processor is configured to:

determine whether the processor is in an idle-standby state; and

determine to store the data in the NVRAM when the processor is in the idle-standby state and to store the data in the DRAM when the processor is not in the idle-standby state.

38. The apparatus of claim 29, wherein to determine whether to store the data in the DRAM or the NVRAM, the at least one processor is configured to:

determine whether the processor is processing data in association with a plurality of subscriber identity module (SIM) cards; and

determine to store the data in the DRAM when the processor is determined to be processing data in association with a plurality of SIM cards.

39. The apparatus of claim 29, wherein the data is loaded into the DRAM or the NVRAM from flash memory resident on a system on a chip (SoC) integrated circuit (IC), the SoC IC including the processor and the flash memory.

40. The apparatus of claim 29, wherein the NVRAM comprises at least one of magnetoresistive random-access memory (MRAM), phase-change random-access memory (PRAM), resistive random-access memory (RRAM), ferroelectric random-access memory (FeRAM), or nano-random-access memory (NRAM).

41. The apparatus of claim 29, wherein the first power state is a high power state and the second power state is a low power state.

42. The apparatus of claim 29, wherein the at least one processor is further configured to access the stored data periodically from one of the DRAM or the NVRAM during the first power state associated with the duty cycle.

43. A non-transitory computer-readable medium storing computer executable code for memory power reduction, comprising code for:

determining whether to store data into a dynamic random-access memory (DRAM) or a non-volatile random-access memory (NVRAM) based on a power consumption by the DRAM in association with refreshing the data in the DRAM and use of the data stored in the DRAM by a processor, based on a power consumption by the NVRAM in association with use of the data stored in the NVRAM by the processor, and based on a duty cycle associated with current drawn in a first power state and a second power state in association with the data, said NVRAM being a type of random-access memory other than flash memory; and

storing the data into one of the DRAM or the NVRAM based on the determination whether to store the data in the DRAM or the NVRAM.