Endurance translation layer (ETL) and diversion of temp files for reduced flash wear of a super-endurance solid-state drive

• US 9,547,589 B2
• Filed: 12/18/2014
• Issued: 01/17/2017
• Est. Priority Date: 06/18/2008
• Status: Active Grant

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Technology, Corporation
• Inventors: Yu, Frank, Ma, Abraham C., Chen, Shimon
• Primary Examiner(s): TSAI, SHENG JEN
• Application Number:
  US14/575,872
• Publication Number:
  US 20150106556A1
• Time in Patent Office: 761 Days
• Field of Search: 711/103
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/765 in solid state disks

Abstract

A flash drive has increased endurance and longevity by reducing writes to flash. An Endurance Translation Layer (ETL) is created in a DRAM buffer and provides temporary storage to reduce flash wear. A Smart Storage Switch (SSS) controller assigns data-type bits when categorizing host accesses as paging files used by memory management, temporary files, File Allocation Table (FAT) and File Descriptor Block (FDB) entries, and user data files, using address ranges and file extensions read from FAT. Paging files and temporary files are never written to flash. Partial-page data is packed and sector mapped by sub-sector mapping tables that are pointed to by a unified mapping table that stores the data-type bits and pointers to data or tables in DRAM. Partial sectors are packed together to reduce DRAM usage and flash wear. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.

Claims

1. An Endurance Translation Layer (ETL) method to increase endurance of a flash memory that has a specified erase-cycle lifetime comprising:

creating an ETL in a dynamic-random-access memory (DRAM) buffer that is controlled by a controller and using the ETL to provide temporary storage to reduce flash wear;

creating a spare/swap area in the DRAM buffer;

operating a controller to use the spare/swap area in the DRAM buffer to merge valid data in a flash memory with new data to generate combined data; and

writing the combined data to the flash memory;

creating a page status table in the DRAM buffer;

operating the controller to use the page status table in the DRAM buffer to record the status of each flash page;

when a flash block is erased, setting the page status of each page in the flash block to an empty page;

when a page is written, changing the page status to a used page;

when the host data writes to a same Logical Page Address, writing data to a new flash page and setting the page status for an old page to a deleted/trimmed page;

when a trim command is received from the host, setting a corresponding page status to a deleted/trimmed page;

when the page is identified as a bad page, setting the page status to a bad page;

during a garbage collection process, not moving pages indicated as deleted/trimmed pages to a new flash block;

creating a spare/swap area in the DRAM buffer;

operating the controller to use the spare/swap area in the DRAM buffer to merge valid data in flash memory and new data to generate combined data;

wherein the page status of each page in a targeted block is examined from the page status table;

wherein valid data page has the page status indicating as a used page;

the page status not indicating as a bad page, an empty page, or a trimmed page;

writing the combined data to the flash memory;

whereby a spare/swap function is performed by the controller using the DRAM buffer rather than the flash memory,

whereby a spare/swap function is performed by the controller using the DRAM buffer rather than the flash memory.

2. The Endurance Translation Layer (ETL) method of claim 1 further comprising:

providing wear-leveling control to flash blocks in the flash memory;

when the controller needs a flash block to write data to through a spare/swap area of the DRAM buffer, checking a block status/erase count table, and selecting a lowest erase count flash block from a list of blocks with an empty block status;

wherein a highest erase count flash block is not selected.

3. The Endurance Translation Layer (ETL) method of claim 1 further comprising:

providing wear-leveling control to flash blocks in the flash memory;

when a device is idle and a maximum erase count has reached a predetermined threshold, selecting a group of targeted used blocks with lowest erase counts and an equal number of targeted empty blocks with highest erase counts using a block status/erase count table, copying data from a lowest erase count flash block to a highest erase count flash block through a spare/swap area of the DRAM buffer, and erasing the lowest erase count flash block;

recycling the lowest erase count flash block;

minimizing a delta of an erase count of each block.

4. An Endurance Translation Layer (ETL) method to increase endurance of a flash memory that has a specified erase-cycle lifetime comprising:

creating an ETL in a dynamic-random-access memory (DRAM) buffer that is controlled by a controller and using the ETL to provide temporary storage to reduce flash wear;

creating a spare/swap area in the DRAM buffer;

operating a controller to use the spare/swap area in the DRAM buffer to merge valid data in a flash memory with new data to generate combined data; and

writing the combined data to the flash memory;

whereby a spare/swap function is performed by the controller using the DRAM buffer rather than the flash memory;

creating a plurality of sub-sector mapping tables stored in the DRAM buffer and accessed by the controller, each sub-sector mapping table comprising a plurality of sector entries selected by a sector number within a page;

wherein a sector entry comprises;

a partial-sector bit that indicates when the entry is a full-sector entry for a full sector of data for the host and when the entry is a partial-sector entry for a) partial sector of data from the host;

a page pointer that points to a page location in the DRAM buffer that stores the full sector of data or the partial sector of data;

when the entry is a full-sector entry, a sector identifier that identifies a sector within the page location;

when the entry is a partial-sector entry, a byte offset that identifies a starting byte location within the page location, and a length that indicates a length of the partial sector of data;

wherein full-sector entries and partial-sector entries are stored in the plurality of sub-sector mapping tables.

5. An Endurance Translation Layer (ETL) method to increase endurance of a flash memory that has a specified erase-cycle lifetime comprising:

creating an ETL in a dynamic-random-access memory (DRAM) buffer that is controlled by a controller and using the ETL to provide temporary storage to reduce flash wear;

creating a spare/swap area in the DRAM buffer;

operating a controller to use the spare/swap area in the DRAM buffer to merge valid data in a flash memory with new data to generate combined data; and

writing the combined data to the flash memory;

whereby a spare/swap function is performed by the controller using the DRAM buffer rather than the flash memory;

creating a mapping table;

wherein an entry in the mapping table comprises;

data-type bits that indicate a type of data stored for the logical address that selected the entry;

a pointer that points to a location in the DRAM buffer when a full page of host data is stored in the DRAM buffer, or points to a location in the flash memory when the full page of host data is stored in the flash memory, wherein the pointer points to a location in the DRAM buffer that stores a sub-sector mapping table in the plurality of sub-sector mapping tables when the host data is a partial page of data;

wherein the data-type bits indicate a data type that is selected from the group consisting of;

a File Allocation Table (FAT) entry;

a File Descriptor Block (FDB) entry;

a paging file created by a memory manager on the host that swaps data from a main memory on the host to a flash drive;

a temporary file identified by a file extension in a FAT entry that indicates a temporary file created by a program executing on the host, the temporary file being deletable upon power off/loss; and

a user file that stores user or application data for a user of the host;

wherein the controller allows user files to be copied to the flash memory but prevents temporary files from being written to the flash memory,

whereby flash wear is reduced by preventing temporary files from being written to the flash memory.

6. An Endurance Translation Layer (ETL) method to increase endurance of a flash memory that has a low specified erase-cycle lifetime comprising:

creating an ETL in a dynamic-random-access memory (DRAM) buffer that is controlled by a controller and using the ETL to provide temporary storage to reduce flash wear;

creating a spare/swap area in the DRAM buffer;

operating a controller to use the spare/swap area in the DRAM buffer to merge valid data in a flash memory with new data to generate combined data; and

writing the combined data to the flash memory;

whereby a spare/swap function is performed by the controller using the DRAM buffer rather than the flash memory;

activating a bad block manager when a block in the flash memory is erased to generate an erased block;

counting a number of un-erased bits in a page in the erased block;

when the number of un-erased bits exceeds a lower threshold and does not exceed a higher threshold, marking the page as a protected page and increasing a number of error-correction code (ECC) bits stored for the protected page;

when the number of un-erased bits exceeds the higher threshold, marking the page as a bad page and not storing host data in the bad page;

repeating the counting and the page marking for all pages in the erased block;

counting a number of bad pages in the erased block;

when the erased block has a number of bad pages that exceeds a block threshold, marking the erased block as a bad block and not storing host data in any pages in the bad block.

7. The Endurance Translation Layer (ETL) method of claim 6 further comprising:

using a data split manager to identify a data-type to be a non-temporary data-type or a temporary data type; and

using a backup power supply to power the DRAM buffer and the flash memory and the controller when power is lost, the backup power supply having a sufficient capacity for the controller to copy non-temporary data in the ETL to the flash memory according to a policy.

8. The Endurance Translation Layer (ETL) method of claim 6 further comprising:

controlling various functions using a packed manager;

managing a data write cache stored in the DRAM buffer;

writing a first write data from the host and a header to a beginning of the data write cache;

writing a new write data from the host and a header next to a previous data in the data write cache;

wherein when an updated write data is received from the host and an old data is in the data write cache, the controller discarding the old data and its header and moving a dirty data behind a location that stored the old data and then appending the updated write data and its header;

wherein when the dirty data has a size of more than a stripe-ready unit and the data write cache is full, the controller writing the stripe-ready unit to the flash memory.

9. The Endurance Translation Layer (ETL) method of claim 6 further comprising:

creating a data write cache area in the DRAM buffer;

recording an access frequency for each Logical-Block Address (LBA);

wherein when the access frequency is larger than a predefined value, the LBA is categorized as a Frequent Accessed (FA), otherwise the LBA is categorized as a Non-Frequent Accessed (NFA);

when the accessed LBA is categorized as a FA, storing data in a FA cache area;

when the accessed LBA is categorized as a NFA, storing data in a NFA cache area;

wherein the NFA cache area has a higher priority to be written to the flash memory and to be overwritten by other FA or NFA LBA accesses.

10. An Endurance Translation Layer (ETL) method to increase endurance of a flash memory that has a low specified erase-cycle lifetime comprising:

creating an ETL in a dynamic-random-access memory (DRAM) buffer that is controlled by a controller and using the ETL to provide temporary storage to reduce flash wear;

creating a spare/swap area in the DRAM buffer;

operating a controller to use the spare/swap area in the DRAM buffer to merge valid data in a flash memory with new data to generate combined data; and

writing the combined data to the flash memory;

whereby a spare/swap function is performed by the controller using the DRAM buffer rather than the flash memory;

using the controller to manage a data write cache stored in the DRAM buffer;

operating an in-line compression circuit and compressing the host writes, for adding a header to compressed data, and updating a compressed mapping table;

wherein the controller further comprises various compress algorithms;

selecting an adequate algorithm to compress write data based on type of data set;

when a data set has an identical data set existing, using the compressed mapping table and pointing to the same compressed data set;

when a data set has a similar data set existing, using the compressed mapping table and pointing to the same compressed data plus using a pointer to point to the delta data;

when a data set has no similar data set existing, moving the compressed data to the DRAM buffer and updating a pointer in the compressed mapping table;

when a data size is not reduced after compression, retaining the original data;

whereby a size of write data is reduced, resulting in fewer writes to the flash memory to prolong flash endurance.