Timing exact design conversions from FPGA to ASIC

• US 9,547,736 B2
• Filed: 07/29/2013
• Issued: 01/17/2017
• Est. Priority Date: 07/08/2002
• Status: Expired due to Term

• Current Assignee: Liberty Patents LLC
• Original Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Inventors: Madurawe, Raminda
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US13/953,666
• Publication Number:
  US 20130311961A1
• Time in Patent Office: 1,268 Days
• Field of Search: 716/116, 716/17, 716/138, 326 38- 41
• US Class Current: 1/1
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts.

Claims

1. A field-programmable gate array (FPGA) design conversion to an application-specific integrated circuit (ASIC), the conversion comprising:

providing an FPGA device and an ASIC device having;

a substantially identical layout;

substantially identical transistors and one or more metal layer layouts; and

substantially identical timing characteristics;

providing a user-configurable memory to program transistors in the FPGA;

providing a mask-configurable memory to program transistors in the ASIC; and

in a processor, converting a user-configurable memory bit pattern, to thereby program the transistors of the FPGA, to a mask-configurable memory pattern comprising a conductive pattern deposited to hard-wire logic connections in an adjacent layer of digital circuits to only Vcc and Vss, wherein the digital circuits comprise the transistors of the ASIC, in order to identically program the transistors of the ASIC.

2. The conversion of claim 1, wherein digital circuits in the FPGA are identical to digital circuits in the ASIC.

3. The conversion of claim 1, wherein interconnects and routing in the FPGA are identical to interconnects and routing in the ASIC.

4. The conversion of claim 1, wherein control signals to program the programmable logic content in the FPGA are identical to control signals to program the programmable logic content in the ASIC.

5. The conversion of claim 4, wherein the user-configurable memory generates the control signals in the FPGA, and wherein the mask-configurable memory generates the control signals in the ASIC.

6. The conversion of claim 1, wherein the FPGA and the ASIC further comprises:

an input, wherein the input is received at an input pad; and

an output, wherein the output is presented at an output pad;

wherein an input to output signal propagation delay is substantially identical between the FPGA and the ASIC.

7. The conversion of claim 1, wherein the memory element in the FPGA further comprises one of:

a fuse link, an anti-fuse capacitor, an SRAM cell, a DRAM cell, a metal optional link, an EPROM cell, an EEPROM cell, a flash cell, a ferro-electric element, an electro-chemical cell, an electromagnetic cell, a carbon nano-tube, an optical element, or a magnetic element.

8. The conversion of claim 1, wherein the mask-configurable memory in the ASIC further comprises a metal wire coupled to a power supply voltage or a ground supply voltage.

9. A device having a design conversion from a field-programmable gate array (FPGA) to an application-specific integrated circuit (ASIC), the device comprising:

a user-configurable element in the FPGA replaced by a mask-configurable element in the ASIC comprising a conductive pattern deposited to hard-wire logic connections in an adjacent layer of digital circuits to only Vcc and Vss, wherein the FPGA and the ASIC have substantially identical transistor layouts and substantially identical timing characteristics.

10. The device of claim 9, wherein the FPGA and the ASIC comprises substantially identical functionality and timing characteristics.