Reverse complement magnetic tunnel junction (MTJ) bit cells employing shared source lines, and related methods

• US 9,548,096 B1
• Filed: 08/26/2015
• Issued: 01/17/2017
• Est. Priority Date: 08/26/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Li, Xia, Lu, Yu, Zhu, Xiaochun
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US14/835,871
• Time in Patent Office: 510 Days
• Field of Search: 365/158, 365/200
• US Class Current: 1/1
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

Reverse complement MTJ bit cells employing shared source lines are disclosed. In one aspect, a 2T2MTJ reverse complement bit cell employing shared source line is provided. Bit cell includes first MTJ and second MTJ. Value of first MTJ is complement of value of second MTJ. First bit line is coupled to top layer of first MTJ, and first electrode of first access transistor is coupled to bottom layer of first MTJ. Second bit line is coupled to bottom layer of second MTJ, and first electrode of second access transistor is coupled to top layer of second MTJ. Word line is coupled to second electrode of first access transistor and second access transistor. Shared source line is coupled to third electrode of first access transistor and second access transistor. Employing shared source line allows the bit cell to be designed with reduced parasitic resistance.

Claims

1. A reverse complement magnetic tunnel junction (MTJ) bit cell, comprising:

a first MTJ;

a second MTJ;

a first electrode of a first access transistor coupled to a bottom layer of the first MTJ;

a first electrode of a second access transistor coupled to a top layer of the second MTJ;

a word line coupled to a second electrode of the first access transistor and a second electrode of the second access transistor;

a first bit line coupled to a top layer of the first MTJ;

a second bit line coupled to a bottom layer of the second MTJ; and

a shared source line coupled to a third electrode of the first access transistor and a third electrode of the second access transistor.

2. The reverse complement MTJ bit cell of claim 1, wherein the reverse complement MTJ bit cell comprises a two (2) transistor, two (2) MTJ (2T2MTJ) reverse complement bit cell.

3. The reverse complement MTJ bit cell of claim 1, wherein:

the first bit line is configured to receive a first read voltage;

the second bit line is configured to receive a second read voltage; and

the shared source line is configured to receive a shared read voltage.

4. The reverse complement MTJ bit cell of claim 1, wherein:

the first bit line is configured to receive a first write voltage;

the second bit line is configured to receive a second write voltage; and

the shared source line is configured to receive a shared write voltage.

5. The reverse complement MTJ bit cell of claim 1, wherein:

the top layer of the first MTJ comprises a free layer of the first MTJ;

the bottom layer of the first MTJ comprises a pinned layer of the first MTJ;

the top layer of the second MTJ comprises a free layer of the second MTJ; and

the bottom layer of the second MTJ comprises a pinned layer of the second MTJ.

6. The reverse complement MTJ bit cell of claim 1, wherein:

the top layer of the first MTJ comprises a pinned layer of the first MTJ;

the bottom layer of the first MTJ comprises a free layer of the first MTJ;

the top layer of the second MTJ comprises a pinned layer of the second MTJ; and

the bottom layer of the second MTJ comprises a free layer of the second MTJ.

7. The reverse complement MTJ bit cell of claim 1, wherein the first access transistor comprises an n-type metal oxide semiconductor (NMOS) transistor, and wherein:

the first electrode of the first access transistor comprises a drain;

the second electrode of the first access transistor comprises a gate; and

the third electrode of the first access transistor comprises a source.

8. The reverse complement MTJ bit cell of claim 1, wherein the second access transistor comprises an n-type metal oxide semiconductor (NMOS) transistor, and wherein:

the first electrode of the second access transistor comprises a drain;

the second electrode of the second access transistor comprises a gate; and

the third electrode of the second access transistor comprises a source.

9. The reverse complement MTJ bit cell of claim 1, wherein the first access transistor comprises a p-type metal oxide semiconductor (PMOS) transistor, and wherein:

the first electrode of the first access transistor comprises a source;

the second electrode of the first access transistor comprises a gate; and

the third electrode of the first access transistor comprises a drain.

10. The reverse complement MTJ bit cell of claim 1, wherein the second access transistor comprises a p-type metal oxide semiconductor (PMOS) transistor, and wherein:

the first electrode of the second access transistor comprises a source;

the second electrode of the second access transistor comprises a gate; and

the third electrode of the second access transistor comprises a drain.

11. The reverse complement MTJ bit cell of claim 1 integrated into an integrated circuit (IC).

12. The reverse complement MTJ bit cell of claim 1 integrated into a device selected from the group consisting of:

a set top box;

an entertainment unit;

a navigation device;

a communications device;

a fixed location data unit;

a mobile location data unit;

a mobile phone;

a cellular phone;

a computer;

a portable computer;

a desktop computer;

a personal digital assistant (PDA);

a monitor;

a computer monitor;

a television;

a tuner;

a radio;

a satellite radio;

a music player;

a digital music player;

a portable music player;

a digital video player;

a video player;

a digital video disc (DVD) player; and

a portable digital video player.

13. A method for accessing a reverse complement magnetic tunnel junction (MTJ) bit cell, comprising:

providing a first access voltage to a first bit line coupled to a top layer of a first MTJ, wherein the first MTJ further comprises a bottom layer coupled to a first electrode of a first access transistor;

providing a second access voltage to a second bit line coupled to a bottom layer of a second MTJ, wherein the second MTJ further comprises a top layer coupled to a first electrode of a second access transistor;

providing a source voltage to a shared source line coupled to a third electrode of the first access transistor and a third electrode of the second access transistor; and

providing an enable voltage to a word line coupled to a second electrode of the first access transistor and a second electrode of the second access transistor.

14. The method of claim 13, wherein accessing the reverse complement MTJ bit cell comprises reading the reverse complement MTJ bit cell, wherein:

providing the first access voltage comprises providing a first read voltage to the first bit line;

providing the second access voltage comprises providing a second read voltage to the second bit line; and

providing the source voltage comprises providing a shared read voltage to the shared source line.

15. The method of claim 13, wherein accessing the reverse complement MTJ bit cell comprises writing the reverse complement MTJ bit cell, wherein:

providing the first access voltage comprises providing a first write voltage to the first bit line;

providing the second access voltage comprises providing a second write voltage to the second bit line; and

providing the source voltage comprises providing a shared write voltage to the shared source line.

16. A reverse complement magnetic tunnel junction (MTJ) bit cell, comprising:

a first MTJ;

a second MTJ;

a first access transistor formed on a substrate, the first access transistor comprising a first electrode electrically coupled to a bottom layer of the first MTJ;

a second access transistor formed on the substrate, the second access transistor comprising a first electrode electrically coupled to a top layer of the second MTJ;

a word line disposed so as to be electrically coupled to a second electrode of the first access transistor and to a second electrode of the second access transistor;

a first bit line disposed in a third metal layer so as to be electrically coupled to a top layer of the first MTJ;

a second bit line disposed in a second metal layer so to as to be electrically coupled to a bottom layer of the second MTJ; and

a shared source line disposed in a first metal layer so as to be electrically coupled to a third electrode of the first access transistor and a third electrode of the second access transistor.

17. The reverse complement MTJ bit cell of claim 16, wherein the reverse complement MTJ bit cell comprises a two (2) transistor, two (2) MTJ (2T2MTJ) reverse complement bit cell.

18. The reverse complement MTJ bit cell of claim 16, wherein:

the top layer of the first MTJ comprises a free layer of the first MTJ;

the bottom layer of the first MTJ comprises a pinned layer of the first MTJ;

the top layer of the second MTJ comprises a free layer of the second MTJ; and

the bottom layer of the second MTJ comprises a pinned layer of the second MTJ.

19. The reverse complement MTJ bit cell of claim 16, wherein:

the top layer of the first MTJ comprises a pinned layer of the first MTJ;

the bottom layer of the first MTJ comprises a free layer of the first MTJ;

the top layer of the second MTJ comprises a pinned layer of the second MTJ; and

the bottom layer of the second MTJ comprises a free layer of the second MTJ.

20. The reverse complement MTJ bit cell of claim 16, wherein the first metal layer is comprised of metal one (M1).

21. The reverse complement MTJ bit cell of claim 16, wherein the second metal layer is comprised of metal two (M2).

22. The reverse complement MTJ bit cell of claim 16, wherein the third metal layer is comprised of metal three (M3).

23. The reverse complement MTJ bit cell of claim 16, wherein the first access transistor comprises an n-type metal oxide semi-conductor (NMOS) transistor, and wherein:

the first electrode of the first access transistor comprises a drain;

the second electrode of the first access transistor comprises a gate; and

the third electrode of the first access transistor comprises a source.

24. The reverse complement MTJ bit cell of claim 16, wherein the second access transistor comprises an n-type metal oxide semi-conductor (NMOS) transistor, and wherein:

the first electrode of the second access transistor comprises a drain;

the second electrode of the second access transistor comprises a gate; and

the third electrode of the second access transistor comprises a source.

25. The reverse complement MTJ bit cell of claim 16 integrated into a device selected from the group consisting of:

a set top box;

an entertainment unit;

a navigation device;

a communications device;

a fixed location data unit;

a mobile location data unit;

a mobile phone;

a cellular phone;

a computer;

a portable computer;

a desktop computer;

a personal digital assistant (PDA);

a monitor;

a computer monitor;

a television;

a tuner;

a radio;

a satellite radio;

a music player;

a digital music player;

a portable music player;

a digital video player;

a video player;

a digital video disc (DVD) player; and

a portable digital video player.

26. A method of manufacturing a reverse complement magnetic tunnel junction (MTJ) bit cell, comprising:

forming a first access transistor on a substrate;

forming a second access transistor on the substrate;

disposing a word line so as to be electrically coupled to a second electrode of the first access transistor and a second electrode of the second access transistor;

disposing a shared source line in a first metal layer such that the shared source line is electrically coupled to a third electrode of the first access transistor and a third electrode of the second access transistor;

disposing a first bit line in a third metal layer;

disposing a second bit line in a second metal layer;

disposing a first MTJ such that a top layer of the first MTJ is electrically coupled to the first bit line and a bottom layer of the first MTJ is electrically coupled to a first electrode of the first access transistor; and

disposing a second MTJ such that a top layer of the second MTJ is electrically coupled to a first electrode of the second access transistor and a bottom layer of the second MTJ is electrically coupled to the second bit line.

27. The method of claim 26, wherein:

disposing the first MTJ comprises disposing the first MTJ such that the top layer of the first MTJ comprises a free layer;

disposing the first MTJ comprises disposing the first MTJ such that the bottom layer of the first MTJ comprises a pinned layer;

disposing the second MTJ comprises disposing the second MTJ such that the top layer of the second MTJ comprises a free layer; and

disposing the second MTJ comprises disposing the second MTJ such that the bottom layer of the second MTJ comprises a pinned layer.

28. The method of claim 26, wherein:

disposing the first MTJ comprises disposing the first MTJ such that the top layer of the first MTJ comprises a pinned layer;

disposing the first MTJ comprises disposing the first MTJ such that the bottom layer of the first MTJ comprises a free layer;

disposing the second MTJ comprises disposing the second MTJ such that the top layer of the second MTJ comprises a pinned layer; and

disposing the second MTJ comprises disposing the second MTJ such that the bottom layer of the second MTJ comprises a free layer.