Memory device comprising an electrically floating body transistor

• US 9,548,119 B2
• Filed: 01/15/2015
• Issued: 01/17/2017
• Est. Priority Date: 01/15/2014
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Han, Jin-Woo, Widjaja, Yuniarto
• Primary Examiner(s): Bernstein, Allison P
• Application Number:
  US14/597,444
• Publication Number:
  US 20150200005A1
• Time in Patent Office: 733 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 15/043 using capacitive charge storage elements
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.

Claims

1. A memory cell comprising:

a silicon-on-insulator (SOI) substrate;

an electrically floating body transistor fabricated on said silicon-on-insulator (SOI) substrate and comprising a first conductivity type selected from p-type conductivity type and n-type conductivity type;

a source line region comprising a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type, said source line region in physical contact with a floating body region of said floating body transistor;

a drain region comprising said second conductivity type in physical contact with said floating body region and spaced apart from said source line region; and

a charge injector region, wherein said charge injection region comprises said second conductivity type and is in physical contact with said floating body region and spaced apart from said source line region and said drain region;

wherein said floating body transistor is configured to have more than one stable state through an application of a bias on said charge injector region; and

wherein said drain region and said source line region are bounded at the bottom by an insulator layer.

2. A memory array comprising a plurality of said memory cells of claim 1, arranged in at least one row and at least one column.

3. The memory cell of claim 1, further comprising a gate positioned in between said source line region and said drain region, above said floating body region.

4. The memory cell of claim 1 configured such that a holding operation on said memory cell does not require any interruption to access to said memory cell.

5. The array of claim 2, comprising a charge injector terminal connected to all of said memory cells in a row or column of said array;

wherein said charge injector terminal is configured to perform a holding operation on all of said memory cells connected to said charge injector terminal in a batch operation, so that no individual selection of one of said memory cells is required to perform the holding operation.

6. The memory cell of claim 1, wherein application of a charge to said charge injector region in performance of a holding operation also increases a size of a memory window of said floating body region.

7. The memory cell of claim 1, further comprising a second charge injection region in contact with said floating body region and spaced apart from said first charge injection region.

8. The memory cell of claim 1, wherein said charge injector region comprises a first charge injector region, said memory cell further comprising a second charge injector region, wherein said first and second charge injector regions are configured to maintain a state of said memory cell.

9. The memory cell of claim 1, wherein a depth of said charge injector region is less than a depth of said drain region and said source line region.

10. The memory cell of claim 1, wherein said charge injector region is less than said depth of said floating body region.

11. The memory cell of claim 3, further comprising a second gate region.

12. The memory cell of claim 11, wherein said second gate region is positioned in between said charge injection region and one of said source line region and said drain region.

13. A memory device comprising the memory cell of claim 1 connected in series to an access device.

14. A memory device comprising the memory cell of claim 1, connected in series to an access device;

wherein said access device comprises;

a body region comprising said first conductivity type;

a second source line region comprising said second conductivity type in contact with said body region;

a second drain region comprising said second conductivity type in contact with said body region and spaced apart from said second source line region; and

a body tap region comprising said first conductivity type in contact with said body region.

15. The memory device of claim 14, wherein said body tap region is configured to apply a bias on said body region.

16. The memory device of claim 13, wherein said memory cell and said access device comprise two transistors each having a same conductivity type.

17. The memory device of claim 13, wherein said memory cell and said access device comprise two transistors each having a different conductivity type.

18. A memory device comprising the memory cell of claim 1, connected in series to an access device;

wherein said access device comprises;

a body region comprising said first conductivity type;

a second source line region comprising said second conductivity type in contact with said body region; and

a second drain region comprising said second conductivity type in contact with said body region and spaced apart from said second source line region.

19. A content addressable memory cell comprising:

the memory cell of claim 1; and

a second floating body transistor;

wherein said first floating body transistor and said second floating body transistor are electrically connected in series through a common node; and

wherein said first floating body transistor and said second floating body transistor store complementary data.

20. A memory cell comprising:

a silicon-on-insulator (SOI) substrate;

an electrically floating body transistor fabricated on said silicon-on-insulator (SOI) substrate;

a drain region in electrical contact with a floating body region of said electrically floating body transistor;

a source line region in electrical contact with said electrically floating body region and spaced from said drain region;

a charge injector region in physical contact with said floating body region;

wherein said floating body region is configured to have more than one stable state through an application of a bias on said charge injector region;

wherein said drain region and said source line region are bounded at the bottom by an insulator layer.

21. The memory cell of claim 20, further comprising a gate positioned between said drain region, said source line region and said charge injector region;

wherein transistors are formed by said charge injector region, said gate, said source line region and said floating body region; and

by said charge injection region, said gate, said drain region and said floating body region; and

at least one of said transistors is used to stably maintain said state of said floating body region, while another of said transistors is used for read and write operations.