Electrical connection for chip scale packaging

• US 9,548,281 B2
• Filed: 10/07/2011
• Issued: 01/17/2017
• Est. Priority Date: 10/07/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yew, Ming-Chih, Lin, Wen-Yi, Li, Fu-Jen, Lin, Po-Yao
• Primary Examiner(s): Slutsker, Julia
• Assistant Examiner(s): GONDARENKO, NATALIA A
• Application Number:
  US13/269,310
• Publication Number:
  US 20130087892A1
• Time in Patent Office: 1,929 Days
• Field of Search: 257737-738, 257/786, 257773-775, 257778-784, 257/621, 257/632, 257/685, 257/741, 438/108, 438/540, 438/612, 438/613, 438/617, 438/637, 438/666, 438/675
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05012 in top view
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05541 Structure
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05555 being circular or elliptic
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/061 Disposition
• CPC Class Codes: H01L 2224/06137 with specially adapted redistribution layers [RDL]
• CPC Class Codes: H01L 2224/06179 Corner adaptations, i.e. disposition of the bonding areas at the corners of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/141 Disposition
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/206 : Length ranges

Abstract

A system and method for providing a post-passivation opening and undercontact metallization is provided. An embodiment comprises an opening through the post-passivation which has a first dimension longer than a second dimension, wherein the first dimension is aligned perpendicular to a chip'"'"'s direction of coefficient of thermal expansion mismatch. By shaping and aligning the opening through the post-passivation layer in this fashion, the post-passivation layer helps to shield the underlying layers from stresses generated from mismatches of the materials'"'"' coefficient of thermal expansion.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having active devices thereon;

a first post-passivation interconnect over the active devices, the semiconductor substrate having a first direction of coefficient of thermal expansion mismatch and a first quadrant, wherein the first post-passivation interconnect comprises;

a first interconnect region, the first interconnect region in line with the first direction of coefficient of thermal expansion mismatch; and

a first landing pad in physical connection with the first interconnect region, the first landing pad having an elliptical shape in plan view;

a second post-passivation interconnect over the active devices, wherein the second post-passivation interconnect comprises;

a second interconnect region; and

a second landing pad in physical connection with the second interconnect region;

a post-passivation layer over the first post-passivation interconnect and the second post-passivation interconnect;

a first opening through the post-passivation layer directly over the first landing pad, the first opening having a first dimension and a second dimension, the second dimension being less than the first dimension, wherein the first dimension and the second dimension are both in a plane parallel with a major surface of the semiconductor substrate, wherein the first dimension is aligned perpendicular to the first direction of coefficient of thermal expansion mismatch, wherein in a plan view the first landing pad extends beyond the first opening in a third direction a first distance and extends beyond the first opening in a fourth direction opposite the third direction a second distance, wherein the third direction and the fourth direction are perpendicular to a length of the first post-passivation interconnect and parallel to a width of the first post-passivation interconnect in the plan view, wherein in plan view the first landing pad extends beyond the first opening in a fifth direction a third distance and extends beyond the first opening in a sixth direction opposite the fifth direction a fourth distance, wherein the fifth direction and sixth direction are parallel to the length of the first post-passivation interconnect and perpendicular to the width of the first post-passivation interconnect in plan view, wherein the third direction and the fourth direction are perpendicular to the second dimension of the first opening, wherein a first sum of the third distance, fourth distance, and second dimension is greater than a second sum of the first distance, second distance, and first dimension; and

a second opening through the post-passivation layer directly over the second landing pad, wherein the first opening and the second opening are both located in the first quadrant, the second opening having a third dimension and a fourth dimension, wherein the fourth dimension is less than the third dimension, wherein the third dimension and the fourth dimension are both in a plane parallel with the major surface of the semiconductor substrate, wherein the third dimension is not parallel with the first dimension, wherein the third dimension is aligned perpendicular to a second direction of coefficient of thermal expansion mismatch different from the first direction of coefficient of thermal expansion mismatch,

wherein the first opening is filled with a first material.

2. The semiconductor device of claim 1, wherein the first material comprises an undercontact metallization layer extending through the first opening.

3. The semiconductor device of claim 1, further comprising a third opening through the post-passivation layer, the third opening being circular in shape.

4. The semiconductor device of claim 1, wherein the first opening is located along an edge of the semiconductor substrate.

5. The semiconductor device of claim 4, wherein the first opening is located at a corner region of the semiconductor substrate and the second opening is located along the edge of the semiconductor substrate.

6. The semiconductor device of claim 4, wherein the second opening is located within an interior region of the semiconductor substrate.

19. The semiconductor device of claim 1, wherein the first material does not exist between the post-passivation layer and the semiconductor substrate.

20. The semiconductor device of claim 1, and wherein the first material extends over the first opening and has a different shape than the first opening in the plan view.

7. A semiconductor device comprising:

a semiconductor substrate having a plurality of active devices thereon;

a metallization layer coupled to at least one of the active devices;

a contact pad disposed on the metallization layer;

a first passivation layer over the contact pad and metallization layer, the first passivation layer being non-planar and conformal to the contact pad;

a first pad opening being formed in the first passivation layer over the contact pad and reaching the contact pad;

a second passivation layer over the first passivation layer, the second passivation layer being planar;

a second pad opening being formed in the second passivation layer over the contact pad and reaching the contact pad, the second pad opening being within and smaller in a width dimension in cross-section than the first pad opening;

a post-passivation interconnect over the plurality of active devices, formed over the second passivation layer, and coupled to the contact pad, the post-passivation interconnect comprising;

a first region having a substantially uniform width in a top down view; and

a landing pad in physical contact and substantially level with the first region and having a non-uniform width in the top down view, the first region electrically coupling the landing pad to the plurality of active devices, the landing pad being elliptical in plan view having a length and width, the length being greater than the width;

a dielectric layer over the post-passivation interconnect;

a first opening through the dielectric layer, wherein the first opening extends to the landing pad, the first opening having a first dimension larger than a second dimension, the first dimension and second dimension being parallel to a major surface of the semiconductor substrate, wherein the first dimension is aligned perpendicular to a first line extending between a center of the semiconductor substrate and a center of the first opening, and wherein the length of the landing pad is within the first line; and

a first undercontact metallization extending into the first opening, the first undercontact metallization being configured to have a solder material formed thereon, the first undercontact metallization extending over an uppermost portion of the dielectric layer, wherein the first undercontact metallization extends to a bottom of the first opening but does not extend between the dielectric layer and the semiconductor substrate.

8. The semiconductor device of claim 7, further comprising a second opening through the dielectric layer, the second opening having a circular shape.

9. The semiconductor device of claim 8, wherein the first opening is located along an outer edge of the semiconductor substrate and the second opening is located within an interior region of the semiconductor substrate.

10. The semiconductor device of claim 8, wherein the first opening is located along an outer edge of the semiconductor substrate and the second opening is located along the outer edge of the semiconductor substrate.

11. The semiconductor device of claim 10, wherein the first opening is located in a corner region of the semiconductor substrate.

12. The semiconductor device of claim 7, further comprising a second opening through the dielectric layer, the second opening having a third dimension larger than a fourth dimension, the third dimension and fourth dimension being parallel to the major surface of the semiconductor substrate, wherein the third dimension is aligned perpendicular to a second line extending between the center of the semiconductor substrate and a center of the second opening.

13. A method of manufacturing a semiconductor device, the method comprising:

forming a passivation layer on a semiconductor substrate, the semiconductor substrate having a plurality of active devices thereon, the plurality of active devices being interposed between the passivation layer and the semiconductor substrate, the semiconductor substrate having a first direction of coefficient of thermal expansion mismatch and a second direction of coefficient of thermal expansion mismatch different from the first direction of coefficient of thermal expansion mismatch;

forming a first opening through the passivation layer after the passivation layer has been completely formed, the first opening having a first length along a first line greater than a first width along a second line, the first length aligned perpendicularly with the first direction of coefficient of thermal expansion mismatch;

forming an undercontact metallization in the first opening and extending over a portion of the passivation layer, wherein the undercontact metallization is in physical contact with a landing pad of a post-passivation interconnect, the landing pad having an elliptical shape in a plan view and located between the passivation layer and the semiconductor substrate, wherein in plan view the landing pad extends from the first opening along the second line further than a circle with a diameter defined by a width of the landing pad along the first line, wherein the width of the landing pad along the first line is greater than the first length of the first opening, wherein the post-passivation interconnect electrically couples the undercontact metallization to the plurality of active devices; and

forming a second opening through the passivation layer in a same quadrant as the first opening, the second opening having a second length greater than a second width, the second length aligned with the second direction of coefficient of thermal expansion mismatch.

14. The method of claim 13, wherein the first direction of coefficient of thermal expansion mismatch is aligned with a line between a center of the first opening and a center of the semiconductor substrate.

15. The method of claim 13, further comprising forming a third opening through the passivation layer, the third opening having a circular shape.

16. The method of claim 15, wherein the first opening is located along an outer edge of the semiconductor substrate.

17. The method of claim 15, wherein the first opening is located in a corner region of the semiconductor substrate.

18. The method of claim 13, further comprising testing to determine the first direction of coefficient of thermal expansion mismatch.