Structure for integration of an III-V compound semiconductor on SOI
First Claim
1. A semiconductor structure comprising:
- a handle substrate of silicon or germanium that is miscut from 2 degrees to 8 degrees towards the <
111>
crystallographic direction or the <
100>
crystallographic direction;
an III-V compound semiconductor pillar extending upward from one region of said handle substrate, wherein said III-V compound semiconductor pillar is in direct contact with a topmost surface of said handle substrate and is surrounded by dielectric material; and
a top semiconductor material portion located over another region of said handle substrate, wherein said top semiconductor material portion is separated from said handle substrate by an insulator layer.
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Abstract
A semiconductor-on-insulator (SOI) substrate is provided that includes a silicon or germanium handle substrate that is miscut from 2 degrees to 8 degrees towards the <111> crystallographic direction or the <100> crystallographic direction. The topmost semiconductor layer is removed from a portion of the SOI substrate, and then a trench having a high aspect ratio is formed within the insulator layer of the SOI substrate and along the <111> crystallographic direction or the <100> crystallographic direction. An III-V compound semiconductor pillar, which includes a lower portion that has a first defect density and an upper portion that has a second defect density that is less than the first defect density, is then formed in the trench.
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Citations
10 Claims
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1. A semiconductor structure comprising:
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a handle substrate of silicon or germanium that is miscut from 2 degrees to 8 degrees towards the <
111>
crystallographic direction or the <
100>
crystallographic direction;an III-V compound semiconductor pillar extending upward from one region of said handle substrate, wherein said III-V compound semiconductor pillar is in direct contact with a topmost surface of said handle substrate and is surrounded by dielectric material; and a top semiconductor material portion located over another region of said handle substrate, wherein said top semiconductor material portion is separated from said handle substrate by an insulator layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification