Structure for integration of an III-V compound semiconductor on SOI

• US 9,548,319 B2
• Filed: 03/10/2015
• Issued: 01/17/2017
• Est. Priority Date: 03/10/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Jagannathan, Hemanth, Reznicek, Alexander
• Primary Examiner(s): Gupta, Raj R
• Application Number:
  US14/643,360
• Publication Number:
  US 20160268310A1
• Time in Patent Office: 679 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A semiconductor-on-insulator (SOI) substrate is provided that includes a silicon or germanium handle substrate that is miscut from 2 degrees to 8 degrees towards the <111> crystallographic direction or the <100> crystallographic direction. The topmost semiconductor layer is removed from a portion of the SOI substrate, and then a trench having a high aspect ratio is formed within the insulator layer of the SOI substrate and along the <111> crystallographic direction or the <100> crystallographic direction. An III-V compound semiconductor pillar, which includes a lower portion that has a first defect density and an upper portion that has a second defect density that is less than the first defect density, is then formed in the trench.

Claims

1. A semiconductor structure comprising:

a handle substrate of silicon or germanium that is miscut from 2 degrees to 8 degrees towards the <

111>

crystallographic direction or the <

100>

crystallographic direction;

an III-V compound semiconductor pillar extending upward from one region of said handle substrate, wherein said III-V compound semiconductor pillar is in direct contact with a topmost surface of said handle substrate and is surrounded by dielectric material; and

a top semiconductor material portion located over another region of said handle substrate, wherein said top semiconductor material portion is separated from said handle substrate by an insulator layer.

2. The semiconductor structure of claim 1, wherein said III-V compound semiconductor pillar comprises a lower portion that has a first defect density and an upper portion that has a second defect density that is less than said first defect density.

3. The semiconductor structure of claim 1, wherein said III-V compound semiconductor pillar is formed along said <

111>

crystallographic direction of said handle substrate.

4. The semiconductor structure of claim 1, wherein said III-V compound semiconductor pillar is formed along said <

100>

crystallographic direction of said handle substrate.

5. The semiconductor structure of claim 1, wherein said semiconductor material portion comprises crystalline silicon.

6. The semiconductor structure of claim 1, wherein said III-V compound semiconductor pillar has an epitaxial relationship with said topmost surface of said handle substrate.

7. The semiconductor structure of claim 1, wherein said III-V compound semiconductor pillar and said semiconductor portion are separated by a trench isolation structure.

8. The semiconductor structure of claim 1, wherein said III-V compound semiconductor pillar has a topmost surface that is coplanar with a topmost surface of said semiconductor material portion.

9. The semiconductor structure of claim 1, wherein said III-V compound semiconductor pillar has a width of 20 nm or less.

10. The semiconductor structure of claim 1, further comprising a first functional gate structure located on an exposed portion of said semiconductor material portion, and a second functional gate structure located on an exposed portion of said III-V compound semiconductor pillar.